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Out-of-Step Prediction Using DQN-Based Disturbance Observer and Its RTDS Verification
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Out-of-Step Prediction Using DQN-Based Disturbance Observer and Its RTDS Verification
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Journal Article
Out-of-Step Prediction Using DQN-Based Disturbance Observer and Its RTDS Verification
2022
Overview
Despite having extensive research dedicated towards designing methodologies for synchronous out-of-step detection, the risk posed by a large-scale power blackout still makes power system protection an active research area. In recent decades, multiple out-of-step detection techniques such as impedance-based relays and equal-area criterion-analysis-based methods have been widely adopted. However, these conventional techniques have been known to suffer from drawbacks that may be attributed to the inherent assumptions of their foundational design principles. Therefore, to alleviate some of the problems faced in the currently adopted techniques, researchers have been studying the implementation of estimation algorithms for synchronous out-of-step detection. Aiming to contribute to this research area, this paper proposes a synchronous out-of-step detection algorithm that uses a deep Q-network-based disturbance observer, robust to measurement noise. Using the disturbance estimation provided by the observer and a separately gathered critical clearing time data of the power grid, a neural network is trained to relate the magnitude of the estimation with the critical clearing time. The trained neural network is then used to provide an estimation of the critical clearing time for the algorithm, which uses the information to predict whether a fault will result in a stable power swing or a synchronous out-of-step detection. The performance of the proposed algorithm is verified through a real-time digital-simulator-based hardware-in-the-loop simulation. The results show that the proposed algorithm can detect synchronous out-of-step prediction by estimating the disturbance resulting from line fault within two cycles and predicting the critical clearing time at sample fault locations within a 3% margin of error.
Publisher
MDPI AG
