Asset Details
Do you wish to reserve the book?
VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application
Do you wish to request the book?
VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application
Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
Journal Article
VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application
2013
Overview
An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.
Publisher
The Institution of Engineering and Technology,Institution of Engineering and Technology
Subject
/ Biological and medical sciences
/ Electrocardiography. Vectocardiography
/ Electrodiagnosis. Electric activity recording
/ Exact sciences and technology
/ Information, signal and communications theory
/ Integrated circuits by function (including memories and processors)
/ Investigative techniques, diagnostic techniques (general aspects)
/ lossless compression algorithm
/ Pathology. Cytology. Biochemistry. Spectrometry. Miscellaneous investigative techniques
/ power
/ Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
/ Signal and communications theory
/ size
/ Telecommunications and information theory
/ VLSI
