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Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits
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Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits
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Journal Article
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits
2014
Overview
This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.
Publisher
The Institution of Engineering and Technology,Institution of Engineering and Technology,John Wiley & Sons, Inc
Subject
/ automatic test pattern generation
/ Design. Technologies. Operation analysis. Testing
/ Electric, optical and optoelectronic circuits
/ Exact sciences and technology
/ multioutput combinational logic cells
/ nanocomplementary metal oxide semiconductor integrated circuits
/ SAT‐based test generation procedure
/ Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
