Journal Article

On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Bonet Zordan, L. H., Badereddine, N., Bosio, A., Dilillo, L., Girard, P., Virazel, A.

2014

Overview

In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.

• Publisher: Springer US,Springer Nature B.V,Springer Verlag
• Subject: Arrays / CAE) and Design / Circuits and Systems / Computer-Aided Engineering (CAD / Defects / Electric power generation / Electrical Engineering / Electronics / Energy consumption / Engineering / Engineering Sciences / Gating and risering / Leakage current / Power consumption / Product testing / Random access memory / Simulation / Test procedures