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Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
by
Locharla, Govinda Rao
, Ari, Samit
, Mahapatra, Kamala Kanta
, Kallur, Sudeendra Kumar
in
Algorithms
/ clock gated implementation
/ clock gating
/ Clocks
/ Clocks & watches
/ CMOS
/ Commutators
/ data rate communication
/ Delay
/ eight‐parallel variable length multipath delay commutator
/ Fast Fourier transformations
/ fast Fourier transforms
/ fifth generation wireless fidelity technology
/ forward‐inverse fast Fourier transform processor
/ Fourier transforms
/ high data rate wireless systems
/ IEEE 802.11ac compliant MU MIMO‐OFDM system
/ inverse transforms
/ Mathematical models
/ Microprocessors
/ MIMO communication
/ MIMO data reordering
/ MIS devices
/ MU MIMO‐OFDM technique
/ multipath delay commutator‐based FFT‐IFFT processor
/ multiuser multiple‐input multiple‐output orthogonal frequency division multiplexing technique
/ OFDM modulation
/ Orthogonal Frequency Division Multiplexing
/ physical layer design
/ pipelined FFT‐IFFT processor
/ power aware computing
/ Power management
/ Scheduling
/ scheduling methodology
/ Special Issue: Selected Papers from the 19th International Symposium on VLSI Design and Test (VDAT)
/ TSMC complementary metal‐oxide‐semiconductor technology
/ Wireless communication
/ wireless LAN
2016
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Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
by
Locharla, Govinda Rao
, Ari, Samit
, Mahapatra, Kamala Kanta
, Kallur, Sudeendra Kumar
in
Algorithms
/ clock gated implementation
/ clock gating
/ Clocks
/ Clocks & watches
/ CMOS
/ Commutators
/ data rate communication
/ Delay
/ eight‐parallel variable length multipath delay commutator
/ Fast Fourier transformations
/ fast Fourier transforms
/ fifth generation wireless fidelity technology
/ forward‐inverse fast Fourier transform processor
/ Fourier transforms
/ high data rate wireless systems
/ IEEE 802.11ac compliant MU MIMO‐OFDM system
/ inverse transforms
/ Mathematical models
/ Microprocessors
/ MIMO communication
/ MIMO data reordering
/ MIS devices
/ MU MIMO‐OFDM technique
/ multipath delay commutator‐based FFT‐IFFT processor
/ multiuser multiple‐input multiple‐output orthogonal frequency division multiplexing technique
/ OFDM modulation
/ Orthogonal Frequency Division Multiplexing
/ physical layer design
/ pipelined FFT‐IFFT processor
/ power aware computing
/ Power management
/ Scheduling
/ scheduling methodology
/ Special Issue: Selected Papers from the 19th International Symposium on VLSI Design and Test (VDAT)
/ TSMC complementary metal‐oxide‐semiconductor technology
/ Wireless communication
/ wireless LAN
2016
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Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
by
Locharla, Govinda Rao
, Ari, Samit
, Mahapatra, Kamala Kanta
, Kallur, Sudeendra Kumar
in
Algorithms
/ clock gated implementation
/ clock gating
/ Clocks
/ Clocks & watches
/ CMOS
/ Commutators
/ data rate communication
/ Delay
/ eight‐parallel variable length multipath delay commutator
/ Fast Fourier transformations
/ fast Fourier transforms
/ fifth generation wireless fidelity technology
/ forward‐inverse fast Fourier transform processor
/ Fourier transforms
/ high data rate wireless systems
/ IEEE 802.11ac compliant MU MIMO‐OFDM system
/ inverse transforms
/ Mathematical models
/ Microprocessors
/ MIMO communication
/ MIMO data reordering
/ MIS devices
/ MU MIMO‐OFDM technique
/ multipath delay commutator‐based FFT‐IFFT processor
/ multiuser multiple‐input multiple‐output orthogonal frequency division multiplexing technique
/ OFDM modulation
/ Orthogonal Frequency Division Multiplexing
/ physical layer design
/ pipelined FFT‐IFFT processor
/ power aware computing
/ Power management
/ Scheduling
/ scheduling methodology
/ Special Issue: Selected Papers from the 19th International Symposium on VLSI Design and Test (VDAT)
/ TSMC complementary metal‐oxide‐semiconductor technology
/ Wireless communication
/ wireless LAN
2016
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Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
Journal Article
Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
2016
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Overview
The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight-parallel multimode (N = 512/256/128/64) multi-path delay commutator-based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU-MIMO-OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre-, post-FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre-transformed data reordering and 11.64 mW for the post-transformed data reordering with an area occupation of 0.7694 mm2 and 0.5111 mm2, respectively.
Publisher
The Institution of Engineering and Technology,John Wiley & Sons, Inc
Subject
/ Clocks
/ CMOS
/ Delay
/ eight‐parallel variable length multipath delay commutator
/ Fast Fourier transformations
/ fifth generation wireless fidelity technology
/ forward‐inverse fast Fourier transform processor
/ high data rate wireless systems
/ IEEE 802.11ac compliant MU MIMO‐OFDM system
/ multipath delay commutator‐based FFT‐IFFT processor
/ multiuser multiple‐input multiple‐output orthogonal frequency division multiplexing technique
/ Orthogonal Frequency Division Multiplexing
/ pipelined FFT‐IFFT processor
/ Special Issue: Selected Papers from the 19th International Symposium on VLSI Design and Test (VDAT)
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