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FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
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FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
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FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System

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FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System
Journal Article

FPGA Based Adaptive Rate and Manifold Pattern Projection for Structured Light 3D Camera System

2018
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Overview
The quality of the captured point cloud and the scanning speed of a structured light 3D camera system depend upon their capability of handling the object surface of a large reflectance variation in the trade-off of the required number of patterns to be projected. In this paper, we propose and implement a flexible embedded framework that is capable of triggering the camera single or multiple times for capturing single or multiple projections within a single camera exposure setting. This allows the 3D camera system to synchronize the camera and projector even for miss-matched frame rates such that the system is capable of projecting different types of patterns for different scan speed applications. This makes the system capturing a high quality of 3D point cloud even for the surface of a large reflectance variation while achieving a high scan speed. The proposed framework is implemented on the Field Programmable Gate Array (FPGA), where the camera trigger is adaptively generated in such a way that the position and the number of triggers are automatically determined according to camera exposure settings. In other words, the projection frequency is adaptive to different scanning applications without altering the architecture. In addition, the proposed framework is unique as it does not require any external memory for storage because pattern pixels are generated in real-time, which minimizes the complexity and size of the application-specific integrated circuit (ASIC) design and implementation.