Dissertation

Dual reference signal post-silicon reconfigurable clock distribution networks

Chattopadhyay, Atanu

2008

Overview

This thesis investigates the use of averaging techniques in the development of clock distribution networks and an on-chip clock skew measurement circuit. Our flexible clock distribution network can be used in both single clock and multiple clock integrated circuit applications. The design moves away from clock trees, using a pair of reference clocks traveling in opposite directions to perform clock synchronization on a daisy-chained (serial) clock distribution line. By synchronizing each local clock edge to a position directly in between the forward and reverse reference clock edges, we demonstrate that sub-10 ps variance in clock arrival times can be achieved between local clocks. The design provides a scalable and simple-to-layout solution with multi-point skew compensation useful for large designs. The system provides the benefits of a closed-loop clock de-skewing solution by compensating for process, temperature and power supply variations, with the power savings of an open-loop solution at run-time. Our technique allows routing switches to be included in the clock path, permitting the post-silicon re-sizing and re-shaping of clock domains. Localized clock switches or a complete chip-wide switch mesh can be used to re-route clock signals—a capability that is impossible without our daisy-chained clock network. We investigate a clock network that emphasizes flexibility and reconfigurability without sacrificing tolerance to clock skew. We show that this approach is realizable with transistor-level schematic and extracted circuit structures in TSMC's 180 nm standard process. We also develop a modeling infrastructure from which we can create a variety of clock network configurations and synthesizable clock network controllers for arbitrary applications using ModelSim and Quartus II. An on-chip clock skew management system to detect and potentially correct clock skew between selected points on an IC is also investigated. Our system, BICSS, aids in the debugging of timing errors that may be discovered during testing due to the added visibility of the on-chip clock signals and can repair otherwise defective dies using high-resolution delay lines in the clock path. BICSS is unique in its ability to detect, measure and compensate for clock skew using a single all-in-one solution.

• Publisher: ProQuest Dissertations & Theses
• Subject: Electrical engineering
• ISBN: 9780494538609, 0494538600