Asset Details
Do you wish to reserve the book?
适配PAICORE2.0的硬件编码转帧加速单元设计
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
适配PAICORE2.0的硬件编码转帧加速单元设计
Do you wish to request the book?
适配PAICORE2.0的硬件编码转帧加速单元设计
Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
Journal Article
适配PAICORE2.0的硬件编码转帧加速单元设计
2024
Overview
为了解决北京大学脉冲神经网络芯片PAICORE2.0类脑终端系统中软件编码和转帧过程速度较慢的问题,提出一种硬件加速方法.通过增加硬件加速单元,将Xilinx ZYNQ的处理系统PS端串行执行的软件编码转帧过程转移到可编程逻辑PL端的数据通路中流水化并行执行.硬件加速单元主要包含高度并行的卷积单元、参数化的脉冲神经元和位宽平衡数据缓冲区等.实验结果表明,该方法在几乎不增加数据通路传输延迟的前提下,可以消除软件编码和转帧过程的时间开销.在CIFAR-10图像分类的例子中,与软件编码和转帧方法相比,硬件编码转帧模块仅增加9.3％的LUT、3.7％的BRAM、2.6％的FF、0.9％的LUTRAM、14.9％的DSP以及14.6％的功耗,却能够实现约8.72倍的推理速度提升.
Publisher
北京大学软件与微电子学院,北京 102600%北京大学集成电路学院,北京 100871%北京大学集成电路学院,北京 100871,北京大学深圳研究生院集成微系统科学工程与应用重点实验室,深圳 518055
We currently cannot retrieve any items related to this title. Kindly check back at a later time.