Dissertation

Automated analysis of discrete event simulations using event pattern mappings

Gennart, Benoit Andre

1991

Overview

Event patterns are a language construct for expressing relationships between specifications made at different levels of a hierarchical design of a concurrent system. This presentation (1) explains the use of event patterns in defining mappings between different levels of a design hierarchy, (2) defines a language for specifying event pattern mappings, and (3) shows how mappings can be used in debugging discrete event simulations. The concurrent system specification language used in this research is VHDL. VAL+ is an annotation language for VHDL, geared toward the specification of event pattern mappings. VAL+ features are its simplicity, its ability to define mappings as well as design constraints, its ability to report both pattern occurrences and incorrect ordering relationships in a simulation, and a semantics suitable for efficient implementation. The VAL+ mapping construct defines the relationship between one event at a (high) level of abstraction and a pattern of events at a (lower) level. To investigate the application of event pattern mappings, a debugger has been implemented and used in analyzing gate level simulations. Using mappings specified in VAL+, the debugger extracts, from a VHDL gate level simulation, simulations at the register transfer level and the instruction level. The higher the simulation level, the smaller the number of events. The mapping definitions help the designer trace a missing event at the instruction level down to one or more missing events at the register transfer level, and similarly from the register transfer level to the gate level. This method allows for fast bug detection and pinpointing.

• Publisher: ProQuest Dissertations & Theses
• Subject: Computer science / Electrical engineering
• ISBN: 9798208116920