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An improved bus-based multiprocessor architecture
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An improved bus-based multiprocessor architecture
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Dissertation
An improved bus-based multiprocessor architecture
1997
Overview
This thesis presents a new, cost effective multiprocessing architecture which can be constructed using off-the-shelf components. The proposed architecture extends the current generation of single-board-computer systems to include a low cost, supplemental interprocessor communication network. The resulting extended single-board-computer multiprocessor (ESBCM) architecture is shown to have improved scalability characteristics and is much more flexible than current multiprocessor designs. It also directly supports many real-time and fault-tolerant constructs not previously supported. Extensive empirical analysis using discrete event simulations and Monte Carlo techniques indicate that the ESBCM architecture will generally outperform standard bus-based multiprocessors.
Publisher
ProQuest Dissertations & Theses
Subject
ISBN
9780591381870, 0591381877
