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In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p–n–p–n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10 −15  J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.

We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p + -i-n + Si nanowire (SiNW) channel and two separate gates. The SiNW FBFET can be reconfigured in the p- or n-channel operation modes via simple control of electric signals. The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection. In contrast to previously reported reconfigurable transistors, our transistor features symmetry of the electrical characteristics for the p- and n-channel operation modes. Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p- and n-type configurations, including the on/off ratios (∼ 10 5 ) and subthreshold swings (1.36-1.78 mV/dec). This novel transistor is a promising candidate for reconfigurable electronics.

Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relatively rare. In this study, we merge reconfigurable logic gates and LIM units to achieve a universal logic-in-memory (ULIM) cell for enabling all basic Boolean logic operations and data storage in a single cell. A ULIM cell consisting of silicon memory devices with reconfigurable n- and p-program modes can reconfigure logic operations within the complete set of Boolean logic operations. Moreover, the ULIM cell exhibits memory behaviors for storing output logic values without supply voltages for a certain period, resulting in zero static power consumption. Hence, this study provides a way to realize high-performance electronics by utilizing the silicon devices with a hybrid function of reconfigurable logic and LIM.

In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme. The inverter comprising p- and n-channel FBFETs in series can be in ternary logic states and retain these states during the hold operation owing to the switching and memory functions of FBFETs. It exhibits a high voltage gain of approximately 73 V/V, logic holding time of 150 s, and reliable endurance of approximately 10 5 . This ternary inverter with memory function demonstrates possibilities for a new computing paradigm in multivalued logic applications.

In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 10 12 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.

In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec –1 and a high ON/OFF current ratio of approximately 10 7 . Logic circuits consisting of NS FBFETs perform binary and ternary logic operations of the inverters and NAND and NOR gates in each circuit and store their outputs under zero-bias conditions. Therefore, NS FBFETs are promising components for next-generation LIM.

In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector–matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p + -n-p-n + device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 10 8 ). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.

The change of electrical performance of amorphous SiZnSnO thin film transistors (a-SZTO TFTs) has been investigated depending on various metal capping layers on the channel layer by causing different contact property. It was confirmed that the change of electrical characteristics was sensitively dependent on the change of the capping layer materials on the same channel layer between the source/drain electrodes. This sensitive change in the electrical characteristics is mainly due to different work function of metal capping layer on the channel layer. The work function of each capping layer material has been analyzed and derived by using Kelvin probe force microscopy and compared with the energy bandgap of the SZTO layer. When the work function of the capping layer is larger than that of the channel layer, electrons are depleted from the channel layer to the capping layer. On the contrary, in the case of using a material having a work function smaller than that of the channel layer, the electrical characteristics were improved because electrons were injected into the channel layer. Based on depletion and injection mechanism caused by different contact barrier between metal capping layer and channel layer, NOT, NAND, and NOR logic circuits have been implemented simply by changing metal capping layer on the channel layer .

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 10 8 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n -channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p -channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.