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Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
by
Kyoungah Cho
, Juhee Jeon
, Sangsig Kim
, Sola Woo
in
639/166/987
/ 639/925/927
/ Bias
/ Feedback
/ Humanities and Social Sciences
/ Medicine
/ multidisciplinary
/ Q
/ R
/ Science
/ Science (multidisciplinary)
/ Simulation
/ Transistors
/ Voltage
2022
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Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
by
Kyoungah Cho
, Juhee Jeon
, Sangsig Kim
, Sola Woo
in
639/166/987
/ 639/925/927
/ Bias
/ Feedback
/ Humanities and Social Sciences
/ Medicine
/ multidisciplinary
/ Q
/ R
/ Science
/ Science (multidisciplinary)
/ Simulation
/ Transistors
/ Voltage
2022
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Do you wish to request the book?
Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
by
Kyoungah Cho
, Juhee Jeon
, Sangsig Kim
, Sola Woo
in
639/166/987
/ 639/925/927
/ Bias
/ Feedback
/ Humanities and Social Sciences
/ Medicine
/ multidisciplinary
/ Q
/ R
/ Science
/ Science (multidisciplinary)
/ Simulation
/ Transistors
/ Voltage
2022
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Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
Journal Article
Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors
2022
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Overview
In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 10
12
and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.
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