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Listless set partitioning embedded block (LSK) and set partitioning embedded block (SPECK) are known for their low complexity and simple implementation. However, the drawback is that these block-based algorithms encode each insignificant subband by a zero. This generates many zeros at earlier passes because the number of significant coefficients at higher bitplanes is likely to be very few in a transformed image. An improved LSK (ILSK) algorithm that codes a single zero to several insignificant subbands is proposed. This reduces the length of the output bit string, encoding/decoding time and dynamic memory requirement at early passes. Furthermore, ILSK algorithm is coupled with discrete Tchebichef transform (DTT). This gives rise to a novel coder named as hierarchical listless DTT (HLDTT). The proposed HLDTT has desirable attributes like full embeddedness for progressive transmission, precise rate control for constant bit rate traffic and low complexity for low power applications. The performance of HLDTT is assessed using peak-signal-to-noise-ratio (PSNR) and structural-similarity-index-metric (SSIM). Extensive simulation conducted on various standard test images shows that HLDTT exhibits significant improvement in PSNR values from lower to medium bit rates. At the same time, HLDTT shows improvement in SSIM values on all bit rates.

This paper presents a sinusoidal extraction controller based three-phase shunt active power line conditioners (APLC) for harmonics and reactive power compensation due to non-linear loads. The proposed sinusoidal extraction controller consists of positive-sequence voltage detector to regulate the distorted supply voltage and instantaneous reactive power (p-q) theory for harmonic extraction. This approach is different from the conventional methods and provides good compensation characteristics in steady state as well as transient states. The shunt active filter is implemented with current controlled voltage source inverter (VSI) and switching signals are generated from hysteresis current controller (HCC). The shunt APLC system is investigated and verified in terms of order of harmonics, V^sub DC^ settling time and various other parameters under non-linear load conditions. [PUBLICATION ABSTRACT]

This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.

The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight-parallel multimode (N = 512/256/128/64) multi-path delay commutator-based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU-MIMO-OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre-, post-FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre-transformed data reordering and 11.64 mW for the post-transformed data reordering with an area occupation of 0.7694 mm2 and 0.5111 mm2, respectively.

This paper proposed a novel Fuzzy Logic Controller (FLC) with Phase Locked Loop (PLL) synchronization based three-phase shunt Active Power Line Conditioners (APLC) for power quality improvements in the transmission and supply grid due to the non-linear loads. The application of the Mamdani-type fuzzy logic is developed and this controller is linguistic description, so it does not require a mathematical calculation. The active power filter is implemented with PWM current controlled voltage source inverter (VSI) and is connected at the point of common coupling for compensating the current harmonics and reactive power. The desired reference current(s) are extracted using FLC with PLL algorithm and PWM-VSI gate switching signals are derivate from hysteresis current controller (HCC). This method maintains the dc-side capacitance voltage of the PWM inverter constant and it is observed less time to settle. The shunt APLC system is investigated and the performances of parameters are verified under different non-linear load conditions. [PUBLICATION ABSTRACT]

This paper presents a shunt active power filter for power quality enhancement in terms of harmonics and reactive-power compensation due to the non-linear loads in the distribution network. The compensation approach uses calculation of real-power (p) losses only, which is simpler and different from the conventional p-q theory. The voltage source inverter based active filter switching pulses are generated from adaptive-Hysteresis Current Controller (HCC). This adaptive-HCC changes the hysteresis-bandwidth according to the instantaneous compensation current variation that is used to optimize the required switching frequency. This would improve the active power filter performances. The three-phase shunt active power filter system is investigated under both steady state and transient conditions with non-linear loads.