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Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.

In WSNs “Wireless Sensor Network” and ad hoc networks, efficient and secure routing protocols are essential to ensure reliable communication and optimal resource utilization. Cluster-based routing is organizing the network into clusters, a designated cluster head manages each cluster, which improves scalability and reduces routing overhead. This approach is highly effective in balancing energy consumption and extending network lifetime, particularly in large-scale networks. Conversely, trust-based routing protocols establishing trust metrics for each node, which are used to make routing decisions in order to prioritize security. This method mitigates the risk of attacks by identifying and isolating malicious nodes, thereby ensuring the integrity and confidentiality of data transmission. The integration of blockchain technology with convolutional neural networks (CNNs) represents a promising frontier in decentralized artificial intelligence (AI). However, this fusion has led to considerable security within both the blockchain and AI communities. Through a detailed comparison of these methodologies, this paper highlights their respective advantages, limitations, and potential applications in term of security and energy. The findings suggest that while cluster-based routing is well-suited for energy-efficient networks with stable topologies, trust-based routing offers superior security features, making it ideal for environments with higher risks of node compromise, and the blockchain associated to the CNN ensure a high security.

This paper proposes a robust control strategy to enhance the stability, speed tracking accuracy, and disturbance rejection of electric vehicles (EVs) powered by Permanent Magnet Synchronous Motors (PMSMs). The strategy aims to design a fuzzy Proportional-Integral (PI) controller based on Takagi-Sugeno (TS) fuzzy modeling, integrating a Line Integral Lyapunov Function (LILF) with an H∞ control approach to ensure both robustness and optimal dynamic performance. The controller gains are optimized using Linear Matrix Inequality (LMI) technique, enabling adaptability under various operating conditions. Simulation results demonstrate the superior performance of the proposed LILF-based controller compared to Linear Quadratic Function (LQF) and traditional PI controllers. Specifically, it achieves a rise time of 6 ms, zero overshoot, and no steady-state error, while effectively eliminating vibrations. In contrast, the PI controller exhibits a 21% overshoot and a steady-state error of 0.24. Additionally, the proposed strategy shows strong resilience to external disturbances, contributing to smoother and more energy-efficient EV operation. The suggested controller offers a useful and efficient solution for real-world EV propulsion systems requiring high precision and robustness.

This paper presents an N-metal-oxide semiconductor (NMOS) rectifier designed for efficient radio frequency (RF) energy harvesting and wireless power transmission in passive ultra-high frequency (UHF) radio frequency identification (RFID) applications. The rectifier's efficiency is improved through an innovative diode with a new block connection, reducing the threshold voltage compared to conventional diode transistors. This enhancement significantly boosts output voltage and efficiency. A seven-stage configuration, based on the proposed diode and optimized via a superposition method, has been evaluated for its ability to increase DC output voltage and power conversion efficiency (PCE), particularly at low RF input power levels. Simulations show a PCE of 63% at 900 MHz with an RF input of -11 dBm, delivering 1.610 V across a 0.518 MQ load. Notably, the rectifier maintains a PCE above 30% across a wide input power range from -32 dBm to -5 dBm, overcoming a key challenge of maintaining efficiency under low input power conditions. The circuit architecture was implemented using standard 180 nm TSMC CMOS technology, showcasing its practical applicability in RFID systems.

Error correcting codes constitute one of the core technologies in telecommunications field, especially digital communication applications. The objective of this paper is to compare performance among new designs of chien search block on the one hand and syndrome architectures on the other hand in error correcting codes. All comparison of all designs is made by computing the number of logic, bit error rate values and number of iteration in the case of syndrome architectures Analysis results show that the performances of the new designs based on both second factorization method and Three-Parallel Syndrome architecture are superior to the performances of traditional designs.

Error correcting codes constitute one of the core technologies in telecommunications field, especially digital communication applications. The objective of this paper is to compare performance among new designs of chien search block on the one hand and syndrome architectures on the other hand in error correcting codes. All comparison of all designs is made by computing the number of logic, bit error rate values and number of iteration in the case of syndrome architectures. Analysis results show that the performances of the new designs based on both second factorization method and Three-Parallel Syndrome architecture are superior to the performances of traditional designs.

This research studies an adaptive neural network with a Dynamic Classifier Selection framework on Field-Programmable Gate Arrays (FPGAs). The evaluations are conducted across three different datasets. By adjusting parameters, the architecture surpasses all models in the ensemble set in accuracy and shows an improvement of up to 8% compared to a singular neural network implementation. The research also emphasizes considerable resource savings of up to 109.28%, achieved via partial reconfiguration rather than a traditional fixed approach. Such improved efficiency suggests that the architecture is ideal for settings limited by computational capacity, like in edge computing scenarios. The collected data highlights the architecture's two main benefits: high performance and real-world application, signifying a notable input to FPGA-based ensemble learning methods.