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Rapid progress has been made in recent years repurposing CMOS fabrication tools to build complex photonic circuits. As the field of silicon photonics becomes more mature, foundry processes will be an essential piece of the ecosystem for eliminating process risk and allowing the community to focus on adding value through clever design. Multi‐project wafer runs are a useful tool to promote further development by providing inexpensive, low‐risk prototyping opportunities to academic and commercial researchers. Compared to dedicated silicon manufacturing runs, multi‐project‐wafer runs offer cost reductions of 100× or more. Through OpSIS, we have begun to offer validated device libraries that allow designers to focus on building systems rather than modifying device geometries. The EDA tools that will enable rapid design of such complex systems are under intense development. Progress is also being made in developing practical optical and electronic packaging solutions for the photonic chips, in ways that eliminate or sharply reduce development costs for the user community. This paper will provide a review of the recent developments in silicon photonic foundry offerings with a focus on OpSIS, a multi‐project‐wafer foundry service offering a silicon photonics platform, including a variety of passive components as well as high‐speed modulators and photodetectors, through the Institute of Microelectronics in Singapore.

Integrated photonics offers the possibility of compact, low energy, bandwidth-dense interconnects for large port count spatial optical switches, facilitating flexible and energy efficient data movement in future data communications systems. To achieve widespread adoption, intimate integration with electronics has to be possible, requiring switch design using standard microelectronic foundry processes and available devices. We report on the feasibility of a switch fabric comprised of ubiquitous silicon photonic building blocks, opening the possibility to combine technologies, and materials towards a new path for switch fabric design. Rather than focus on integrating all devices on a single silicon chip die to achieve large port count optical switching, this work shifts the focus towards innovative packaging and integration schemes. In this work, we demonstrate 1×8 and 8×1 microring-based silicon photonic switch building blocks with software control, providing the feasibility of a full 8×8 architecture composed of silicon photonic building blocks. The proposed switch is fully non-blocking, has path-independent insertion loss, low crosstalk, and is straightforward to control. We further analyze this architecture and compare it with other common switching architectures for varying underlying technologies and radices, showing that the proposed architecture favorably scales to very large port counts when considering both crosstalk and architectural footprint. Separating a switch fabric into functional building blocks via multiple photonic integrated circuits offers the advantage of piece-wise manufacturing, packaging, and assembly, potentially reducing the number of optical I/O and electrical contacts on a single die. Photonic switches: No roadblocks on the ring route Ring-shaped silicon photonic switches offer compact geometries at the micron-scale for superior on-chip integration and scalability. The resonant nature of these devices allows for excellent noise isolation down to a single wavelength. Integrated circuits with many ‘microrings’ have been developed recently. Dessislava Nikolova, David M. Calhoun, and researchers at Columbia University and Coriant ATG propose that coupling several such ‘microring integrated circuits’ into a combination of multiplexing and demultiplexing arrays could yield ultrafast optical switches. In the team’s architecture, each combination of two circuits filters a single optical wavelength. Keeping only two microrings per port on resonance through voltage adjustments enables scalable, port-to-port communication without detrimental crosstalk effects. A prototype 8×8 switching device featuring microring circuits with multiplexing and demultiplexing functionality demonstrates the feasibility of the team’s approach and its compatibility with existing semiconductor manufacturing processes.

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform.

We demonstrate open-eye 224G PAM4 transmission in a 1.6T-DR8 PIC implementing low-V silicon-organic hybrid modulators (VL < 0.5 V-mm) with >80 3 dB GHz bandwidth and a variant capable of 400G/ (> 110 GHz) for 3.2T-DR8. Both PIC variants use commercial crosslinkable organic electro-optic materials.

Advances in deep neural networks (DNNs) are transforming science and technology. However, the increasing computational demands of the most powerful DNNs limit deployment on low-power devices, such as smartphones and sensors -- and this trend is accelerated by the simultaneous move towards Internet-of-Things (IoT) devices. Numerous efforts are underway to lower power consumption, but a fundamental bottleneck remains due to energy consumption in matrix algebra, even for analog approaches including neuromorphic, analog memory and photonic meshes. Here we introduce and demonstrate a new approach that sharply reduces energy required for matrix algebra by doing away with weight memory access on edge devices, enabling orders of magnitude energy and latency reduction. At the core of our approach is a new concept that decentralizes the DNN for delocalized, optically accelerated matrix algebra on edge devices. Using a silicon photonic smart transceiver, we demonstrate experimentally that this scheme, termed Netcast, dramatically reduces energy consumption. We demonstrate operation in a photon-starved environment with 40 aJ/multiply of optical energy for 98.8% accurate image recognition and <1 photon/multiply using single photon detectors. Furthermore, we show realistic deployment of our system, classifying images with 3 THz of bandwidth over 86 km of deployed optical fiber in a Boston-area fiber network. Our approach enables computing on a new generation of edge devices with speeds comparable to modern digital electronics and power consumption that is orders of magnitude lower.

Large port count spatial optical switches will facilitate flexible and energy efficient data movement in future data communications systems, especially if they are capable of nanosecond-order reconfiguration times. In this work, we demonstrate an 8x8 microring-based silicon photonic switch with software controlled switching. The proposed switch architecture is modular as it assembles multiple identical components with multiplexing/demultiplexing functionalities. The switch is fully non-blocking, has path independent insertion loss, low crosstalk and is straightforward to control. A scalability analysis shows that this architecture can scale to very large port counts. This work represents the first demonstration of real-time firmware controlled switching with silicon photonics devices integrated at the chip scale.

We present a 30 GHz silicon photonic platform that includes low-loss passive components, high-speed modulators and Ge-on-Si photodetectors. The platform is available to the community as part of the OpSIS-IME multi-project-wafer foundry service. We conclude with a proposal for a fully CMOS-compatible optical isolator based on multistage phase modulation.

Long COVID (LC) is a common chronic health condition that impairs daily functioning and social connections. This is the first randomized clinical trial to directly compare the effect of two Intermittent Fasting regimens on LC symptoms. The main objectives of this 10-week randomized cross-over trial are to compare the efficacy and safety of 4 weeks of 1–2 day fasting plus a restricted diet vs 4 weeks of mild time-restricted eating (TRE) and a restricted diet in reducing patient-reported LC symptoms. After a 2-week run-in, subjects were randomized to treatment A (TRE) or treatment B (Fasting) for 4 weeks. Subjects then crossed over to the other treatment for 4 weeks. The median fasting duration was 38 h (night-day-night), and the mean duration was 42 h. Symptoms were assessed via weekly online surveys. Primary outcomes were changes in LC symptom severity scores (LC-Scores) and in the number of LC symptoms (numLCsym) between treatments. Secondary outcomes were changes in LC-Scores and numLCsym over the 10-week trial. Fasting was superior to TRE alone in reducing LC-Scores (p = 0.008). The numLCsym decreased − 5.0 during the Fasting 4 weeks vs − 1.4 in the TRE 4 weeks (p = 0.002). Altogether, the 10-week regimen of a no-sugar diet, TRE and Fasting decreased the mean LC-Score by 51.8% (p < 0.0001) from 37.8 to 18.2. Similarly, numLCsym decreased from 20.5 to 12.2, a decrease of 40.6% (p < 0.0001). No major adverse safety events were recorded. Both intermittent fasting interventions decreased symptoms over the 10-week trial but the more intense fasting regimen was significantly better. Trial registration : ClinicalTrials.gov Identifier NCT06214455.