Explore the vast range of titles available.

Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques and digital signatures have been applied to protect and authenticate relevant information. However, with the advent of quantum computers and quantum algorithms, classical cryptographic techniques have been in danger of collapsing because quantum computers can solve complex problems in polynomial time. Stemming from that risk, researchers worldwide have stepped up research on post-quantum algorithms to resist attack by quantum computers. In this review paper, we survey studies in recent years on post-quantum cryptography (PQC) and provide statistics on the number and content of publications, including a literature overview, detailed explanations of the most common methods so far, current implementation status, implementation comparisons, and discussion on future work. These studies focused on essential public cryptography techniques and digital signature schemes, and the US National Institute of Standards and Technology (NIST) launched a competition to select the best candidate for the expected standard. Recent studies have practically implemented the public key encryption/key encapsulation mechanism (PKE/KEM) and digital signature schemes on different hardware platforms and applied various optimization measures based on other criteria. Along with the increasing number of scientific publications, the recent trend of PQC research is increasingly evident and is the general trend in the cryptography industry. The movement opens up a promising avenue for researchers in public key cryptography and digital signatures, especially on algorithms selected by NIST.

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

This paper presents an all-digital fractional-N phase-locked loop (ADPLL) operating in the 2.86–3.2 GHz range, optimized for IoT and high-frequency RF transceiver applications demanding stringent phase noise performance, fast settling time, and high integration capability. The key innovation lies in the introduction of a bandpass delta-sigma time-to-digital converter (BPDSTDC) that achieves high-resolution phase detection, an extended detection range of ±2π, and superior noise-shaping characteristics, completely eliminating the complex calibration procedures typically required in conventional TDC designs. The proposed architecture synergistically combines the BPDSTDC with digital down-conversion blocks to extract phase error at baseband, a divider chain integrated with phase interpolators achieving 1/4 fractional resolution to suppress in-band quantization noise, and a wide-bandwidth digital loop filter (>1 MHz) ensuring fast dynamic response and robust stability. The bandpass delta-sigma modulator is implemented with compact resonator structures and a flash quantizer, achieving an optimal balance among resolution, power consumption, and silicon area. The incorporation of highly linear phase interpolators extends fractional frequency synthesis capability without requiring complex digital-to-time converters (DTCs), significantly reducing design complexity and calibration overhead. Fabricated in a 180-nm CMOS technology, the proposed chip demonstrates robust measured performance. The band-pass delta-sigma TDC achieves a low integrated rms timing noise of 183 fs within a 1-MHz bandwidth. Leveraging this low TDC noise, the complete ADPLL exhibits a measured in-band phase noise of −120 dBc/Hz at a 1-MHz offset for a 3.2-GHz output frequency while operating with a loop bandwidth exceeding 1 MHz. This corresponds to a normalized phase noise of −216 dBc/Hz. The system operates from a 1.8-V supply and consumes 10 mW, achieving competitive performance compared with prior noise-shaping TDC-based all-digital PLLs.

This paper proposed an adaptive bandwidth Phase-Locked Loop (PLL) that integrates integer-N and fractional-N switching for energy-efficient RF synthesis in IoT and mobile applications. The architecture exploits wide-bandwidth integer-N mode for rapid lock acquisition, then seamlessly transitions to narrow-bandwidth fractional-N mode for high-resolution synthesis and noise optimization. The architecture features a bandwidth-reconfigurable loop filter with intelligent switching control that monitors phase error dynamics. A novel adaptive digital noise filter mitigates ΔΣ quantization noise, replacing conventional synchronous delay lines. The multi-loop structure incorporates a high-resolution digital phase detector to enhance frequency accuracy and minimize jitter across both operating modes. With 180 nm CMOS technology, the PLL consumes 13.2 mW, while achieving −119 dBc/Hz in-band phase noise and 1 psrms integrated jitter. With an operating frequency range at 2.9–3.2 GHz from a 1.8 V supply, the circuit achieves a worst case fractional spur of −62.7 dBc, which corresponds to a figure of merit (FOM) of −228.8 dB. Lock time improvements of 70% are demonstrated compared to single-mode implementations, making it suitable for high-precision, low-power wireless communication systems requiring agile frequency synthesis.

Substitution boxes (S-Boxes) are the core components of modern block ciphers, responsible for introducing the essential nonlinearity that protects against attacks like linear and differential cryptanalysis. For an 8-bit S-Box, the highest possible nonlinearity for a balanced Boolean function is 116. The best results previously reported in the literature achieved an average nonlinearity of 114.5 across the coordinate Boolean functions of 8 × 8 S-boxes. Our proposed method surpasses this record, producing S-boxes whose coordinate functions exhibit an average nonlinearity of 116. This is a significant achievement as it reaches the best result to date for the nonlinearity of the coordinate Boolean functions of an S-Box. Our S-Box generation method is based on multiplication over the field GF(24) and 4×4 component S-Boxes. The approach is also highly effective, capable of producing a large number of S-Boxes with good cryptographic properties. Other cryptographic criteria, such as BIC, SAC, DAP, and LAP, though not fully optimal, remain within acceptable ranges when compared with other reported designs. In addition, a side-channel attack evaluation is presented, covering both parameter analysis and experimental results on a real system when applying the proposed S-Box in the AES algorithm. These results make it a leading solution for block cipher design.

In modern embedded systems, security issues including side‐channel attacks (SCAs) are becoming of paramount importance since the embedded devices are ubiquitous in many categories of consumer electronics. Recently, deep learning (DL) has been introduced as a new promising approach for profiled and non‐profiled SCAs. This paper proposes and evaluates the applications of different DL techniques including the Convolutional Neural Network and the multilayer perceptron models for non‐profiled attacks on the AES‐128 encryption implementation. Especially, the proposed network is fine‐tuned with different number of hidden layers, labelling techniques and activation functions. Along with the designed models, a dataset reconstruction and labelling technique for the proposed model has also been performed for solving the high dimension data and imbalanced dataset problem. As a result, the DL based SCA with our reconstructed dataset for different targets of ASCAD, RISC‐V microcontroller, and ChipWhisperer boards has achieved a higher performance of non‐profiled attacks. Specifically, necessary investigations to evaluate the efficiency of the proposed techniques against different SCA countermeasures, such as masking and hiding, have been performed. In addition, the effect of the activation function on the proposed DL models was investigated. The experimental results have clarified that the exponential linear unit function is better than the rectified linear unit in fighting against noise generation‐based hiding countermeasure.

The Number Theoretic Transform (NTT) has been widely used to speed up polynomial multiplication in lattice-based post-quantum algorithms. All NTT operands use modular arithmetic, especially modular multiplication, which significantly influences NTT hardware implementation efficiency. Until now, most hardware implementations used Digital Signal Processing (DSP) to multiply two integers and optimally perform modulo computations from the multiplication product. This paper presents a customized Lattice-DSP (L-DSP) for modular multiplication based on the Karatsuba algorithm, Vedic multiplier, and modular reduction methods. The proposed L-DSP performs both integer multiplication and modular reduction simultaneously for lattice-based cryptography. As a result, the speed and area efficiency of the L-DSPs are 283 MHz for 77 SLICEs, 272 MHz for 87 SLICEs, and 256 MHz for 101 SLICEs with the parameters q of 3329, 7681, and 12,289, respectively. In addition, the N−1 multiplier in the Inverse-NTT (INTT) calculation is also eliminated, reducing the size of the Butterfly Unit (BU) in CRYSTAL-Kyber to about 104 SLICEs, equivalent to a conventional multiplication in the other studies. Based on the proposed DSP, a Point-Wise Matrix Multiplication (PWMM) architecture for CRYSTAL-Kyber is designed on a hardware footprint equivalent to 386 SLICEs. Furthermore, this research is the first DSP designed for lattice-based Post-quantum Cryptography (PQC) modular multiplication.

This paper introduces a high-efficiency buck converter designed for a wide load range, targeting low-power applications in medical devices, smart homes, wearables, IoT, and technology utilizing WiFi and Bluetooth. To achieve high efficiency across varying loads, the proposed converter employs a low-power adaptive on-time (AOT) controller that ensures output voltage stability and seamless mode transitions. An adaptive comparator (ACP) with variable output impedance is introduced, offering a variable DC gain and bandwidth to be suitable for different load conditions. A negative-level shifter (NLS) circuit, with its swing ranging from −0.5 V to the battery voltage (VBAT), is proposed to control the smaller power p-MOS transistors. By using an NLS, the chip area, which is mostly occupied by power CMOS transistors, is reduced while the power efficiency is improved, particularly under a heavy load. A status time detector (STD) block which provides control signals to the ACP and NLS for optimized power consumption is added to identify load conditions (heavy, light, ultra-light). By employing a 180 nm CMOS technology, the active chip area occupies about 0.31 mm2. With an input voltage range of 2.8–3.3 V, the controller’s current consumption ranges from 1.2 μA to 16 μA, corresponding to the output load current varying from 12 μA to 120 mA. Although the output load can vary, the output voltage is regulated at 1.2 V with a ripple between 3 and 12 mV. The proposed design achieves a peak efficiency of 96.2% under a heavy load with a switching frequency of 1.3 MHz.

Substitution boxes (S-Boxes) function as essential nonlinear elements in contemporary cryptographic systems, offering robust protection against cryptanalytic attacks. This study presents a novel technique for generating compact 8-bit S-Boxes based on multiplication in the Galois Field GF(24). The goal of this method is to create S-Boxes with low hardware implementation cost while ensuring cryptographic properties. Experimental results indicate that the suggested S-Boxes achieve a nonlinearity value of 112, matching the AES S-Box. They also maintain other cryptographic properties, such as the Bit Independence Criterion (BIC), the Strict Avalanche Criterion (SAC), Differential Approximation Probability, and Linear Approximation Probability, within acceptable security thresholds. Notably, compared to existing studies, the proposed S-Box architecture demonstrates enhanced hardware efficiency, significantly reducing resource utilization in implementations. Specifically, the implementation cost of the S-Box consists of 31 XOR gates, 32 two-input AND gates, 6 two-input OR gates, and 2 MUX21s. Moreover, this work provides a thorough assessment of the S-Box, covering cryptographic properties, side channel attacks, and implementation aspects. Furthermore, the study estimates the quantum resource requirements for implementing the S-Box, including an analysis of CNOT, Toffoli, and NOT gate counts.