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This study presents a time-difference amplifier (TDA) based on adjustable current sources. The proposed amplifier uses a phase detection circuit, delay element, and current source architecture for time-difference (i.e., delay) amplification. It includes a reset circuit that prevents the capacitors in the current sources from charging and discharging simultaneously. In addition, an adjustable current source control increases the range of input time difference. The TDA design is implemented in TSMC 40-nm technology with 964.24 × 961.81  µm 2 overall chip area and 209.42 × 84.76  µm 2 core area. The TDA achieves the widest time-difference input range of ± 13,730 ps, less than 4% gain error, the lowest supply voltage, and the highest FOM compared to prior TDAs.

Low-power and high-speed calculation is very important nowadays for energy-efficient demand of electronic devices. With the usage of ANT (All-N-transistor) logic, the speed constraint caused by PMOS transistors can be overcome through an auxiliary current path across NMOS transistors. This study presents a 800-MHz 28.8-mW 8-bit carry look-ahead adder (CLA) using ANT logic implemented on chip. FinFET technology is utilized to improve carrier mobility and increase device speed. R-C parasitic capacitance in FinFET devices is considered in the analysis of the delay time for the 8-bit CLA to improve PDP (power-delay product). The proposed design is implemented in 16-nm FinFET process with core area of 206.403 × 152.506 μm2. It has the lowest normalized PDP at 60 pF load by far.

An ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. This work demonstrates an ultra low power SRAM on silicon, which is featured with single‐ended cells, supply voltage selection circuit for each memory column, and a PDP reduction circuit. The measurement result shows that it attains a record low 1.0 fJ energy per bit.