Journal Article

A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Lin, Yu‐Cheng, Wang, Chua‐Chin, Tseng, I‐Ting, Chiu, Yi‐Jen, Jose, Oliver Lexter July A., Sangalang, Ralph Gerard B.

2023

Overview

An ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. This work demonstrates an ultra low power SRAM on silicon, which is featured with single‐ended cells, supply voltage selection circuit for each memory column, and a PDP reduction circuit. The measurement result shows that it attains a record low 1.0 fJ energy per bit.

• Publisher: John Wiley & Sons, Inc
• Subject: Circuits / CMOS / digital integrated circuits / Electric potential / Energy / logic design / low‐power electronics / memory architecture / Prototypes / Silicon / Static random access memory / Transistors / VLSI / Voltage