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Spiking neural networks (SNNs) promise to bridge the gap between artificial neural networks (ANNs) and biological neural networks (BNNs) by exploiting biologically plausible neurons that offer faster inference, lower energy expenditure, and event-driven information processing capabilities. However, implementation of SNNs in future neuromorphic hardware requires hardware encoders analogous to the sensory neurons, which convert external/internal stimulus into spike trains based on specific neural algorithm along with inherent stochasticity. Unfortunately, conventional solid-state transducers are inadequate for this purpose necessitating the development of neural encoders to serve the growing need of neuromorphic computing. Here, we demonstrate a biomimetic device based on a dual gated MoS 2 field effect transistor (FET) capable of encoding analog signals into stochastic spike trains following various neural encoding algorithms such as rate-based encoding, spike timing-based encoding, and spike count-based encoding. Two important aspects of neural encoding, namely, dynamic range and encoding precision are also captured in our demonstration. Furthermore, the encoding energy was found to be as frugal as ≈1–5 pJ/spike. Finally, we show fast (≈200 timesteps) encoding of the MNIST data set using our biomimetic device followed by more than 91% accurate inference using a trained SNN. The implementation of spiking neural network in future neuromorphic hardware requires hardware encoder analogous to the sensory neurons. The authors show a biomimetic dual-gated MoS 2 field effect transistor capable of encoding analog signals into stochastic spike trains at energy cost of 1–5 pJ/spike.

The recent decline in energy, size and complexity scaling of traditional von Neumann architecture has resurrected considerable interest in brain-inspired computing. Artificial neural networks (ANNs) based on emerging devices, such as memristors, achieve brain-like computing but lack energy-efficiency. Furthermore, slow learning, incremental adaptation, and false convergence are unresolved challenges for ANNs. In this article we, therefore, introduce Gaussian synapses based on heterostructures of atomically thin two-dimensional (2D) layered materials, namely molybdenum disulfide and black phosphorus field effect transistors (FETs), as a class of analog and probabilistic computational primitives for hardware implementation of statistical neural networks. We also demonstrate complete tunability of amplitude, mean and standard deviation of the Gaussian synapse via threshold engineering in dual gated molybdenum disulfide and black phosphorus FETs. Finally, we show simulation results for classification of brainwaves using Gaussian synapse based probabilistic neural networks. Designing large-scale hardware implementation of Probabilistic Neural Network for energy efficient neuromorphic computing systems remains a challenge. Here, the authors propose an hardware design based on MoS2/BP heterostructures as reconfigurable Gaussian synapses enabling EEG patterns recognition.

Incipient ferroelectricity bridges traditional dielectrics and true ferroelectrics, enabling advanced electronic and memory devices. Firstly, we report incipient ferroelectricity in freestanding SrTiO 3 nanomembranes integrated with monolayer MoS 2 to create multifunctional devices, demonstrating stable ferroelectric order at low temperatures for cryogenic memory devices. Our observation includes ultra-fast polarization switching (~10 ns), low switching voltage (<6 V), over 10 years of nonvolatile retention, 100,000 endurance cycles, and 32 conductance states (5-bit memory) in SrTiO 3 -gated MoS 2 transistors at 15 K and up to 100 K. Additionally, we exploit room-temperature weak polarization switching, a feature of incipient ferroelectricity, to construct a physical reservoir for pattern recognition. Our results showcase the potential of utilizing perovskite material properties enabled by advancements in freestanding film growth and heterogeneous integration, for diverse functional applications. Notably, the low 180 °C thermal budget for fabricating the 3D-SrTiO 3 /2D-MoS 2 device stack enables the integration of diverse materials into silicon complementary metal-oxide-semiconductor technology, addressing challenges in compute-in-memory and neuromorphic applications. Sen et al. report the stacking of a perovskite incipient ferroelectric nanomembrane with atomically thin 2D material for a back-end-of-line compatible ferroelectric-like field effect transistors, functioning as a cryogenic memory at 15 K and as an inference engine at room temperature.

Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed performance and low power consumption. However, scaling SRAM cells to advanced technology nodes poses significant challenges. Three-dimensional (3D) integration offers a promising solution for reinstating SRAM scaling by vertically stacking devices, thereby reducing the physical footprint. In this study, we demonstrate approximately 40% reduction in cell area and improved interconnect length for 3D SRAM cells constructed from field-effect transistors (FETs) based on monolayer MoS 2 , compared to the planar design. Using the layout for the 450 nm technology node, our 2-tier 3D SRAM design achieves better integration density than the planar 350 nm node. Furthermore, we project up to 70% reduction in cell area for 3-tier 3D SRAM cells, closely matching the cell area of the planar 250 nm node. We have successfully realized 1 kilobit of planar SRAM and 2-tier 3D SRAM cell arrays occupying areas of 0.0358 mm² and 0.0251 mm², respectively, each comprising 6144 MoS 2 FETs. Finally, we project the footprint advantage for 3D SRAM cells at scaled technology nodes. Our demonstration highlights the potential of 3D integration of 2D FETs in advancing SRAM technology. The downscaling process of conventional static random-access memory (SRAM) cells has recently slowed down, posing challenges for future electronic devices. Here, the authors demonstrate ~40% reduction in cell area and improved interconnect length for 2-tier 3D-integrated SRAM cells based on 2D MoS 2 transistors.

While defects are undesirable for the reliability of electronic devices, particularly in scaled microelectronics, they have proven beneficial in numerous quantum and energy-harvesting applications. However, their potential for new computational paradigms, such as neuromorphic and brain-inspired computing, remains largely untapped. In this study, we harness defects in aggressively scaled field-effect transistors based on two-dimensional semiconductors to accelerate a stochastic inference engine that offers remarkable noise resilience. We use atomistic imaging, density functional theory calculations, device modeling, and low-temperature transport experiments to offer comprehensive insight into point defects in WSe 2 FETs and their impact on random telegraph noise. We then use random telegraph noise to construct a stochastic encoder and demonstrate enhanced inference accuracy for noise-inflicted medical-MNIST images compared to a deterministic encoder, utilizing a pre-trained spiking neural network. Our investigation underscores the importance of leveraging intrinsic point defects in 2D materials as opportunities for neuromorphic computing. This study demonstrates how point defects in 2D semiconductors can be harnessed for neuromorphic computing. By using random telegraph noise in WSe 2 field-effect transistors, the researchers improve inference accuracy of noise-inflicted medical images.

In-sensor processing, which can reduce the energy and hardware burden for many machine vision applications, is currently lacking in state-of-the-art active pixel sensor (APS) technology. Photosensitive and semiconducting two-dimensional (2D) materials can bridge this technology gap by integrating image capture (sense) and image processing (compute) capabilities in a single device. Here, we introduce a 2D APS technology based on a monolayer MoS 2 phototransistor array, where each pixel uses a single programmable phototransistor, leading to a substantial reduction in footprint (900 pixels in ∼0.09 cm 2 ) and energy consumption (100s of fJ per pixel). By exploiting gate-tunable persistent photoconductivity, we achieve a responsivity of ∼3.6 × 10 7  A W −1 , specific detectivity of ∼5.6 × 10 13  Jones, spectral uniformity, a high dynamic range of ∼80 dB and in-sensor de-noising capabilities. Further, we demonstrate near-ideal yield and uniformity in photoresponse across the 2D APS array. Low-power and compact active pixel sensor (APS) matrices are desired for resource-limited edge devices. Here, the authors report a small-footprint APS matrix based on monolayer MoS 2 phototransistors arrays exhibiting spectral uniformity, reconfigurable photoresponsivity and de-noising capabilities at low energy consumption.

Graphene has a range of properties that makes it suitable for building devices for the Internet of Things. However, the deployment of such devices will also likely require the development of suitable graphene-based hardware security primitives. Here we report a physically unclonable function (PUF) that exploits disorders in the carrier transport of graphene field-effect transistors. The Dirac voltage, Dirac conductance and carrier mobility values of a large population of graphene field-effect transistors follow Gaussian random distributions, which allow the devices to be used as a PUF. The resulting PUF is resilient to machine learning attacks based on predictive regression models and generative adversarial neural networks. The PUF is also reconfigurable without any physical intervention and/or integration of additional hardware components due to the memristive properties of graphene. Furthermore, we show that the PUF can operate with ultralow power and is scalable, stable over time and reliable against variations in temperature and supply voltage. Disorder in the charge carrier transport of graphene-based field-effect transistors can be used to construct physically unclonable functions that are secure and can withstand advanced computational attacks.

The Internet of Things (IoT) is experiencing rapid and accelerating expansion, with edge devices producing staggering amounts of data at an exponential rate. This surge necessitates the development of more efficient and robust computing architectures to handle the immense data flow, as traditional cloud-based computations introduce latency and security vulnerabilities. Artificial neural networks (ANNs) are increasingly required to process these vast amounts of data and extract meaningful insights. However, despite their advancements and contributions to modern computing, ANNs still fall short compared to biological neural networks (BNNs) in terms of energy efficiency, multifunctionality, and adaptability. Remarkably, the human brain performs complex computations while consuming a mere 20W of power, thus inspiring the field of neuromorphic computing. This thesis explores the frontier of neuromorphic computing, focusing on BNNs, the next generation of ANNs capable of reproducing neuronal temporal dynamics with high fidelity. We present three innovative methodologies for the hardware implementation of BNNs, leveraging the potential of two-dimensional (2D) materials, particularly transition-metal dichalcogenides (TMDCs) such as MoS2, to achieve multifunctional field-effect transistors (FETs) and realize energy-efficient computation.Using a commercial silicon photodiode for sensing and introducing a biomimetic dual-gated MoS2FET that transforms the sensed analog input into stochastic spike trains, we demonstrate three distinct encoding methods: rate-based, spike timing, and spike count-based. This approach consumed just 1-5 pJ per spike, which is remarkable. When the encoded spikes was fed to an SNN trained on the MNIST dataset classification task, we observed an accuracy of ~91%.Next, we built a medium-scale integrated circuit comprising 21 photosensitive 2D monolayer MoS2Memtransistor. The circuit incorporates two consecutive three-stage inverters and an XOR logic gate, capable of sensing input light stimulus and encoding it into spike time-based signals. This setup mimics retinal ganglion cells by encoding light intensities through sporadic bursts of activity, with the time-to-first spike indicating illumination levels. Governed by non-volatile memory and analog programmability, the photo encoder exhibited adaptive spiking behavior, consuming energy in the order of microjoules for the entire process.Learning from the first two approaches, we developed a BNN that integrates multiple pixels and enhances energy efficiency. This was realized through MoS2-based optoelectronic, computational, and programmable FETs. This network emulates crucial brain operations, including sensing, encoding, learning, forgetting, and inference. The BNN demonstrated both long-term potentiation (LTP) and long-term depression (LTD), mimicking synaptic plasticity seen in biological systems.These approaches display considerable improvements in energy efficiency, scalability, and flexibility compared to traditional silicon-based neuromorphic counterparts. Leveraging 2D materials and integrated circuits for in-memory sensing and computing can help overcome the von Neumann bottlenecks. Our approach, while accurately emulating neuronal biological functions, enables advanced AI capabilities in resource-limited edge devices. This thesis lays a cornerstone for future advancements in intelligent and adaptive electronic systems, poised to cater to the ever-growing demands of the IoT era. Our work opens the doors to revolutionary, energy-efficient, neuromorphic computer architecture.

Incipient ferroelectricity bridges traditional dielectrics and true ferroelectrics, enabling advanced electronic and memory devices. Firstly, we report incipient ferroelectricity in freestanding SrTiO nanomembranes integrated with monolayer MoS to create multifunctional devices, demonstrating stable ferroelectric order at low temperatures for cryogenic memory devices. Our observation includes ultra-fast polarization switching (~10 ns), low switching voltage (<6 V), over 10 years of nonvolatile retention, 100,000 endurance cycles, and 32 conductance states (5-bit memory) in SrTiO -gated MoS transistors at 15 K and up to 100 K. Additionally, we exploit room-temperature weak polarization switching, a feature of incipient ferroelectricity, to construct a physical reservoir for pattern recognition. Our results showcase the potential of utilizing perovskite material properties enabled by advancements in freestanding film growth and heterogeneous integration, for diverse functional applications. Notably, the low 180 °C thermal budget for fabricating the 3D-SrTiO /2D-MoS device stack enables the integration of diverse materials into silicon complementary metal-oxide-semiconductor technology, addressing challenges in compute-in-memory and neuromorphic applications.

In-sensor processing, which can reduce the energy and hardware burden for many machine vision applications, is currently lacking in state-of-the-art active pixel sensor (APS) technology. Photosensitive and semiconducting two-dimensional (2D) materials can bridge this technology gap by integrating image capture (sense) and image processing (compute) capabilities in a single device. Here, we introduce a 2D APS technology based on a monolayer MoS phototransistor array, where each pixel uses a single programmable phototransistor, leading to a substantial reduction in footprint (900 pixels in ∼0.09 cm ) and energy consumption (100s of fJ per pixel). By exploiting gate-tunable persistent photoconductivity, we achieve a responsivity of ∼3.6 × 10  A W , specific detectivity of ∼5.6 × 10  Jones, spectral uniformity, a high dynamic range of ∼80 dB and in-sensor de-noising capabilities. Further, we demonstrate near-ideal yield and uniformity in photoresponse across the 2D APS array.