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In the absence of a new transistor technology to replace CMOS, design specialization has emerged as one of the most immediate options for achieving high-performance computing [...].In the absence of a new transistor technology to replace CMOS, design specialization has emerged as one of the most immediate options for achieving high-performance computing [...].

Addressing the intrinsic charge transport limitation of metal oxides has been of significance for pursuing viable PEC water splitting photoelectrodes. Growing a photoelectrode with conductive nanoobjects embedded in the matrix is promising for enhanced charge transport but remains a challenge technically. We herein show a strategy of embedding laser generated nanocrystals in BiVO 4 photoanode matrix, which achieves photocurrent densities of up to 5.15 mA cm −2 at 1.23 V RHE (from original 4.01 mA cm −2 ) for a single photoanode configuration, and 6.22 mA cm −2 at 1.23 V RHE for a dual configuration. The enhanced performance by such embedding is found universal owing to the typical features of laser synthesis and processing of colloids (LSPC) for producing ligand free nanocrystals in desired solvents. This study provides an alternative to address the slow bulk charge transport that bothers most metal oxides, and thus is significant for boosting their PEC water splitting performance. While photoelectrochemical water splitting offers a low-cost, integrated means to generate fuel from light, poor charge carrier transport limits performances. Here, authors embed laser-synthesized colloids in bismuth vanadate photoanodes to boost charge carrier mobilities and enhance photocurrents.

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS 2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS 2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS 2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 10 5 and on-state current of 250 μA/μm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process. The simultaneous scaling down of the channel length and gate length of 2D transistors remains challenging. Here, the authors report a self-alignment process to fabricate vertical MoS 2 transistors with sub-1 nm gate length and sub−50 nm channel length, exhibiting on-off ratios over 10 5 and on-state currents of 250 μA/μm at 4 V bias.

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm 2 , and highest on-off ratio up to 2 × 10 5 , which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices. Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length.

Using a between-subjects experimental design with 660, this study investigated the impact of exposure and non-exposure to fact-checking on people’s rectifying behaviors in response to COVID-19 fake news. We found that participants who read COVID-19 fake news accompanied by true fact-checking information believed that the news stories had a greater impact on others than on themselves. This phenomenon is commonly known as the third-person effect (TPE). When exposed to COVID-19 fake news with fact-checking information (vs. fake news with no fact-checking information), youths perceived a less negative influence on themselves and consequently showed weaker intentions to correct fake news on social media. Conversely, they perceived that the fake news had a greater negative influence on others, leading to stronger support for regulating fake news. This study contributes to the existing literature on the third-person effect and fact-checking of fake news in non-Western social media environments.

The objective of this study was to investigate the impact of electro-acupuncture (EA) on sepsis-related intestinal injury and its relationship with macrophage polarization. A sepsis model was established using cecal ligation and puncture (CLP) to assess the effectiveness of EA. The extent of pathological injury was evaluated using Chiu's score, the expression of ZO-1 and Ocludin, and the impact on macrophage polarization was examined through flow cytometry and immunofluorescence staining. The expression of spermidine, one type of polyamine, and ornithine decarboxylase (ODC) was measured using ELISA and PCR. Once the efficacy was determined, a polyamine depletion model was created, and the role of polyamines was reassessed by evaluating efficacy and observing macrophage polarization. EA treatment reduced the Chiu's score and increased the expression of ZO-1 and Ocludin in the intestinal tissue of septic mice. It inhibited the secretion of IL-1β and TNF-α, promoted the polarization of M2-type macrophages, increased the secretion of IL-10, and upregulated the expression of Arg-1, spermidine, and ODC. However, after depleting polyamines, the beneficial effects of EA on alleviating intestinal tissue damage and modulating macrophage polarization disappeared. The mechanism underlying the alleviation of intestinal injury associated with CLP-induced sepsis by EA involves with the promotion of M2-type macrophage polarization mediated by spermidine expression.

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS 2 transistors within a small vertical footprint, corresponding to a device density over 10 8  cm −2 . Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations. Vertical transistors based on 2D semiconductors have the potential to reduce the footprint of electronic circuits, but their high-density integration remains challenging. Here, the authors report a vertical lamination approach for realizing high-density MoS 2 vertical sidewall transistors.

Primary kidney neuroendocrine tumors (NETs) are rare renal malignancies. However, detecting and monitoring neuroendocrine neoplasms remains challenging because of their nonspecific nature. We herein present a case involving a 53-year-old woman who experienced episodes of intermittent abdominal pain, dizziness, and nausea for a period of 5 days. Computed tomography urography revealed a small (approximately 19- × 16-mm) nodular shadow in the left kidney. The nodular shadow exhibited slightly lower density than the surrounding tissue as well as enhancement, with a portion protruding into the renal sinus region. Histological and immunohistochemical analyses of the biopsy specimen from the mass indicated a well-differentiated NET. After analysis of this case, we performed a literature review and herein discuss various techniques for imaging and pathological diagnosis of renal NETs. Additionally, we provide insights into the treatment options and prognosis for affected patients. By combining this case study with the existing published literature, we aim to offer a valuable reference for clinicians treatment patients diagnosed with renal NETs.

This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register–transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on field-programmable gate arrays (FPGAs). The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of the results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL design.

In this paper, a filterless 32-tupling millimeter wave generation scheme based on eight MZMs is proposed. The system has an upper and lower parallel two-branch structure. The upper branch consists of two subsystems Sub-A and Sub-B in cascade, each subsystem contains four MZMs, and the MZMs are all operating at maximum transfer point (MATP). Sub-A mainly generates ±8th order optical sideband signal as the incident light signal of Sub-B. After modulation of Sub−B, the output signal is mainly ±16th order optical sideband signal containing the central optical carrier component. The optical attenuator (OATT) and optical phase shifter (OPS) of the lower branch are used to regulate the phase and amplitude of the optical carrier. The upper and lower branches are coupled, and the central optical carrier component is superimposed and cancelled so only the ±16th order optical sideband signal is retained. Finally, the 32-tupling frequency millimeter is generated by the photodiode (PD) receiver after photoelectric detection which receives and generates a 32-tupling frequency millimeter wave signal. The simulation results show that the 160 GHz millimeter wave signal can be obtained by driving the MZM with a 5 GHz RF signal, and the optical sideband suppression ratio (OSSR) and the RF sideband suppression ratio (RFSSR) are 52.6 dB and 44.75 dB, respectively. Theoretical analysis and simulation experiments are carried out for the proposed scheme which proves the feasibility of the scheme.