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The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies. The challenges and opportunities for the design of field-effect transistors are discussed and a vision of future transistors and potential innovation opportunities is provided.

The development of next-generation electronics requires scaling of channel material thickness down to the two-dimensional limit while maintaining ultralow contact resistance 1 , 2 . Transition-metal dichalcogenides can sustain transistor scaling to the end of roadmap, but despite a myriad of efforts, the device performance remains contact-limited 3 – 12 . In particular, the contact resistance has not surpassed that of covalently bonded metal–semiconductor junctions owing to the intrinsic van der Waals gap, and the best contact technologies are facing stability issues 3 , 7 . Here we push the electrical contact of monolayer molybdenum disulfide close to the quantum limit by hybridization of energy bands with semi-metallic antimony ( 01 1 ̅ 2 ) through strong van der Waals interactions. The contacts exhibit a low contact resistance of 42 ohm micrometres and excellent stability at 125 degrees Celsius. Owing to improved contacts, short-channel molybdenum disulfide transistors show current saturation under one-volt drain bias with an on-state current of 1.23 milliamperes per micrometre, an on/off ratio over 10 8 and an intrinsic delay of 74 femtoseconds. These performances outperformed equivalent silicon complementary metal–oxide–semiconductor technologies and satisfied the 2028 roadmap target. We further fabricate large-area device arrays and demonstrate low variability in contact resistance , threshold voltage, subthreshold swing, on/off ratio, on-state current and transconductance 13 . The excellent electrical performance, stability and variability make antimony ( 01 1 ̅ 2 ) a promising contact technology for transition-metal-dichalcogenide-based electronics beyond silicon. The electrical contact of two-dimensional transistors is pushed close to the quantum limit by hybridization of the energy bands with antimony; the contacts have low contact resistance and excellent stability.

Memristor-enabled neuromorphic computing systems provide a fast and energy-efficient approach to training neural networks 1 – 4 . However, convolutional neural networks (CNNs)—one of the most important models for image recognition 5 —have not yet been fully hardware-implemented using memristor crossbars, which are cross-point arrays with a memristor device at each intersection. Moreover, achieving software-comparable results is highly challenging owing to the poor yield, large variation and other non-ideal characteristics of devices 6 – 9 . Here we report the fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs, which integrate eight 2,048-cell memristor arrays to improve parallel-computing efficiency. In addition, we propose an effective hybrid-training method to adapt to device imperfections and improve the overall system performance. We built a five-layer memristor-based CNN to perform MNIST 10 image recognition, and achieved a high accuracy of more than 96 per cent. In addition to parallel convolutions using different kernels with shared inputs, replication of multiple identical kernels in memristor arrays was demonstrated for processing different inputs in parallel. The memristor-based CNN neuromorphic system has an energy efficiency more than two orders of magnitude greater than that of state-of-the-art graphics-processing units, and is shown to be scalable to larger networks, such as residual neural networks. Our results are expected to enable a viable memristor-based non-von Neumann hardware solution for deep neural networks and edge computing. A fully hardware-based memristor convolutional neural network using a hybrid training method achieves an energy efficiency more than two orders of magnitude greater than that of graphics-processing units.

Ultra-scaled transistors are of interest in the development of next-generation electronic devices 1 – 3 . Although atomically thin molybdenum disulfide (MoS 2 ) transistors have been reported 4 , the fabrication of devices with gate lengths below 1 nm has been challenging 5 . Here we demonstrate side-wall MoS 2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS 2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 10 5 and subthreshold swing values down to 117 mV dec –1 . Simulation results indicate that the MoS 2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore’s law of the scaling down of transistors for next-generation electronics. Ultra-scaled transistors based on two-dimensional MoS 2 with physical gate lengths of 0.34 nm are reported, which show relatively good electrical characteristics and can be switched off.

The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal–oxide–semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref.  1 ). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm −1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V −1 . Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit. A two-dimensional field-effect transistor made of indium selenide is shown to outperform state-of-the-art silicon-based transistors, operating at lower supply voltage and achieving record high transconductance and ballistic ratio.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Memristors hold promise for massively-parallel computing at low power. Aguirre et al. provide a comprehensive protocol of the materials and methods for designing memristive artificial neural networks with the detailed working principles of each building block and the tools for performance evaluation.

Rapid digital technology advancement has resulted in a tremendous increase in computing tasks imposing stringent energy efficiency and area efficiency requirements on next-generation computing. To meet the growing data-driven demand, in-memory computing and transistor-based computing have emerged as potent technologies for the implementation of matrix and logic computing. However, to fulfil the future computing requirements new materials are urgently needed to complement the existing Si complementary metal–oxide–semiconductor technology and new technologies must be developed to enable further diversification of electronics and their applications. The abundance and rich variety of electronic properties of two-dimensional materials have endowed them with the potential to enhance computing energy efficiency while enabling continued device downscaling to a feature size below 5 nm. In this Review, from the perspective of matrix and logic computing, we discuss the opportunities, progress and challenges of integrating two-dimensional materials with in-memory computing and transistor-based computing technologies.This Review discusses the recent progress and future prospects of two-dimensional materials for next-generation nanoelectronics.

Graphene and two-dimensional materials (2DM) remain an active field of research in science and engineering over 15 years after the first reports of 2DM. The vast amount of available data and the high performance of device demonstrators leave little doubt about the potential of 2DM for applications in electronics, photonics and sensing. So where are the integrated chips and enabled products? We try to answer this by summarizing the main challenges and opportunities that have thus far prevented 2DM applications. Graphene and related two-dimensional (2D) materials have remained an active field of research in science and engineering for over fifteen years. Here, the authors investigate why the transition from laboratories to fabrication plants appears to lag behind expectations, and summarize the main challenges and opportunities that have thus far prevented the commercialisation of these materials.

Triboelectrification is a well-known phenomenon that commonly occurs in nature and in our lives at any time and any place. Although each and every material exhibits triboelectrification, its quantification has not been standardized. A triboelectric series has been qualitatively ranked with regards to triboelectric polarization. Here, we introduce a universal standard method to quantify the triboelectric series for a wide range of polymers, establishing quantitative triboelectrification as a fundamental materials property. By measuring the tested materials with a liquid metal in an environment under well-defined conditions, the proposed method standardizes the experimental set up for uniformly quantifying the surface triboelectrification of general materials. The normalized triboelectric charge density is derived to reveal the intrinsic character of polymers for gaining or losing electrons. This quantitative triboelectric series may serve as a textbook standard for implementing the application of triboelectrification for energy harvesting and self-powered sensing. Triboelectric charging is a well-known phenomenon, but triboelectric polarization has only been ranked qualitatively. Here the authors develop a quantified triboelectric series for a wide range of polymers by measuring triboelectric charge density with respect to a liquid metal at well-defined conditions.

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration. This Review explores adopting 2D semiconductors to overcome the scaling bottleneck of Si-based electronics. Recent trends and potential approaches for the development of 2D materials as a channel are discussed. Following this, the prerequisites, obstacles and feasible technologies for integrating contacts and gate dielectrics with 2D semiconductor-based channels are examined. The Review also provides an industrial perspective towards facilitating monolithic 3D integration.