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Availability and accessibility of data objects in a reasonable time is a main issue in distributed systems like cloud computing services. As a result, the reduction of data-related operation times in distributed systems such as data read/write has become a major challenge in the development of these systems. In this regard, replicating the data objects on different servers is one commonly used technique. In general, replica placement plays an essential role in the efficiency of distributed systems and can be implemented statically or dynamically. Estimation of the minimum number of data replicas and the optimal placement of the replicas is an NP-complete optimization problem. Hence, different heuristic algorithms have been proposed for optimal replica placement in distributed systems. Reducing data processing costs as well as the number of replicas, and increasing the reliability of the replica placement algorithms are the main goals of this research. This paper presents a discrete and swarm-evolutionary method using a combination of shuffle-frog leaping and genetic algorithms to data-replica placement problems in distributed systems. The experiments on the standard dataset show that the proposed method reduces data access time by up to 30% with about 14 replicas; whereas the generated replicas by the GA and ACO are, respectively, 24 and 30. The average reduction in data access time by GA and ACO 21% and 18% which shows less efficiency than the SFLA–GA algorithm. Regarding the results, the SFLA–GA converges on the optimal solution before the 10th iteration, which shows the higher performance of the proposed method. Furthermore, the standard deviation among the results obtained by the proposed method on several runs is about 0.029, which is lower than other algorithms. Additionally, the proposed method has a higher success rate than other algorithms in the replica placement problem.

One of the main problems of big distributed systems, like IoT, is the high access time to data objects. Replicating the data objects on various servers is a traditional strategy. Replica placement, which can be implemented statically or dynamically, is generally crucial to the effectiveness of distributed systems. Producing the minimum number of data copies and placing them on appropriate servers to minimize access time is an NP-complete optimization problem. Various heuristic techniques for efficient replica placement in distributed systems have been proposed. The main objectives of this research are to decrease the cost of data processing operations, decrease the number of copies, and improve the accessibility of the data objects. In this study, a discretized and group-based gray wolf optimization algorithm with swarm and evolutionary features was developed for the replica placement problem. The proposed algorithm includes swarm and evolutionary features and divides the wolves’ population into subgroups, and each subgroup was locally searched in a different solution space. According to experiments conducted on the standard benchmark dataset, the suggested method provides about a 40% reduction in the data access time with about five replicas. Also, the reliability of the suggested method during different executions is considerably higher than the previous methods.

A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.

In this article, we design a family of scale-free networks and study its random target access time and weighted spanning trees through the eigenvalues of transition weight matrix. First, we build a type of fractal network with a weight factor and a parameter . Then, we obtain all the eigenvalues of its transition weight matrix by revealing the recursive relationship between eigenvalues in every two consecutive time steps and obtain the multiplicities corresponding to these eigenvalues. Furthermore, we provide a closed-form expression of the random target access time for the network studied. The obtained results show that the random target access is not affected by the weight; it is only affected by parameters and . Finally, we also enumerate the weighted spanning trees of the studied networks through the obtained eigenvalues.

Nowadays, System on Chip (SOC) based devices such as smartphones, tablets, cameras, and others are commonly used. The cost of these devices is determined by the expenses associated with their manufacturing and testing. In modern manufacturing technology, SOC-based devices have more cores embedded within them. However, testing these numerous cores thoroughly can be quite expensive and can sometimes cost more than the manufacturing itself. To make these devices more affordable for people from economically weaker backgrounds, it is necessary to come up with an efficient testing strategy that can help reduce the costs. In this study, we introduce a new method of testing the SOC incompletely instead of testing it thoroughly. This method involves compromising on the test quality, which may result in errors in the output. Incomplete testing is performed only for those cores of the SOC that can tolerate such errors. For example, incomplete testing is performed for the cores that are responsible for multimedia applications such as image or video display, where a slight compromise in the quality can be tolerated by human eyes. This incomplete testing helps to reduce the Test Power Consumption (TP), Test Access Time (TAT), and Test Data Volume (TDV) while compromising with the Fault Coverage (FC).

One of the key issues with large distributed systems, such as IoT platforms, is gaining timely access to data objects. As a result, decreasing the operation time of reading and writing data in distributed communication systems become essential demands for asymmetric system. A common method is to replicate the data objects across multiple servers. Replica placement, which can be performed statically or dynamically, is critical to the effectiveness of distributed systems in general. Replication and placing them on the best available data servers in an optimal manner is an NP-complete optimization problem. As a result, several heuristic strategies for replica placement in distributed systems have been presented. The primary goals of this research are to reduce the cost of data access time, reduce the number of replicas, and increase the reliability of the algorithms for placing replicas. In this paper, a discretized heuristic algorithm with artificial individuals and a hybrid imitation method were developed. In the proposed method, particle and gray-wolf-based individuals use a local memory and velocity to search for optimal solutions. The proposed method includes symmetry in both local and global searches. Another contribution of this research is the development of the proposed optimization algorithm for solving the data object replication problem in distributed systems. Regarding the results of simulations on the standard benchmark, the suggested method gives a 35% reduction in data access time with about six replicates. Furthermore, the standard deviation among the results obtained by the proposed method is about 0.015 which is lower than the other methods in the same experiments; hence, the method is more stable than the previous methods during different executions.

In ultra deep submicron technologies the process variation makes a vital impact on the design. The favorable device characteristic of FinFET avails them as a popular contender for a replacement of CMOS technologies. An optimal approach to increase the access time of a 6T-SRAM cell based on 22 nm FinFET technology is presented in this paper. The approach considers the statistical variation of supply voltage (Vdd) and their corresponding access time variation (read and write) due to technological transform. The spice code is developed and analyzed using HSPICE EDA tool. The simulation results of the read and write access time are evaluated using HSPICE and with Custom WaveView. The results show 11.057 and 12.233 ps for read and write access time at Vdd = 0.80 V which is the nominal voltage for 22 nm FinFET. The power consumption of the 6T-SRAM cell based on the proposed technique is 0.140 mW (at Vdd = 0.80 V) which is explored using Monte Carlo simulation in HSPICE.

Accesses Per Cycle (APC), Concurrent Average Memory Access Time (C-AMAT), and Layered Performance Matching (LPM) are three memory performance models that consider both data locality and memory assess concurrency. The APC model measures the throughput of a memory architecture and therefore reflects the quality of service (QoS) of a memory system. The C-AMAT model provides a recursive expression for the memory access delay and therefore can be used for identifying the potential bottlenecks in a memory hierarchy. The LPM method transforms a global memory system optimization into localized optimizations at each memory layer by matching the data access demands of the applications with the underlying memory system design. These three models have been proposed separately through prior efforts. This paper reexamines the three models under one coherent mathematical framework. More specifically, we present a new memory- centric view of data accesses. We divide the memory cycles at each memory layer into four distinct categories and use them to recursively define the memory access latency and concurrency along the memory hierarchy. This new perspective offers new insights with a clear formulation of the memory performance considering both locality and concurrency. Consequently, the performance model can be easily understood and applied in engineering practices. As such, the memory-centric approach helps establish a unified mathematical foundation for model-driven performance analysis and optimization of contemporary and future memory systems.

The valuation of time is one of the most important public policy issues in project cost-benefit analysis. This paper estimates the value of airport access time and time variability in developing countries with a case study of Nanjing, China. An international meta-analysis is being used to identify the factors that may affect heterogeneity in the value of travel time. Regression models are then established for the prediction of the value of travel time. The results provide some new insights into the impacts of survey region, traffic mode, and trip purpose on the value of travel time. Considering the significant influencing factors that were obtained, stated preference surveys are designed and used to collect data on preferred arrival time and decision choice under various hypothetical situations. A multivariate regression model is used with the data to explore the significant factors that influence the travelers’ preferred arrival time. Mixed logit models are developed to estimate the value of airport access time, value of schedule delay early, and value of schedule delay late by incorporating the effects of travel delay variability on users’ scheduling costs. The tax system is being used to illustrate the contribution of different income groups to social funds, which also calculates the social value of airport access time, social value of schedule delay early, and social value of schedule delay late. The results identify the significant factors that may affect the valuation of airport access time and provide reasonable estimates for these values. The findings also bring new enlightenment on the effects of the variation of airport access time.

Wireless sensor network protocols with limited power resources seek access mechanisms to ensure network efficiency and scalability. Both time division multiple access (TDMA) and code division multiple access (CDMA) have provided partial solutions. While TDMA provides collision-free scheduling under dynamic traffic, it wastes power resources. While CDMA supports parallel transmissions, it ignores processing costs and interference, resulting in loss of access control for verification processes, exposing the network to channel fragmentation. In this paper, we leverage TDMA and CDMA to produce a hybrid protocol that combines the features of structured slots and parallel tokens, along with a lightweight blockchain framework (PoA/PBFT-lite) for verifying slot and token assignments. This ensures fast and secure packet access at the lowest possible cost, increasing network reliability and performance. 500 randomly distributed sensor nodes were used to conduct simulations over an area of 500 square meters. Simulation results showed that the proposed algorithm reduced the average access time to 110 ms, compared to 220 and 180 ms for both traditional TDMA and CDMA protocols, while increasing the packet delivery rate to 97.8% and the data transfer rate to 260 kbps. Simulation results also showed an improvement in energy reduction of 0.25 J per node, in addition to improving the network lifetime to 1280 and 2120 cycles for the first and last nodes, respectively. The results demonstrate the proposed approach as a promising method for sensor networks, demonstrating its scalability and robustness.