Explore the vast range of titles available.

With advances in space, nuclear, and defense industries, the susceptibility of semiconductor integrated circuits (ICs) to radiation has increased. Radiation-induced degradation and malfunctioning of IC performance can lead to system failure, leading to significant damage. To address this limitation, this study employed mixed-stage modeling and simulation (M&S) techniques to evaluate the reliability of complementary metal-oxide semiconductor application-specific ICs (ASICs) in radiation environments. Radiation-hardened IC chips were designed and fabricated using layout modification techniques based on M&S. The ASIC, which includes the D-latch and Operational Amplifier (Op-Amp) circuits, was validated for resistance up to a total ionizing dose of 20 kGy(Si). The proposed radiation-hardened ICs demonstrated stable performance even in radiation-exposed environments, ensuring reliable operation under such conditions. The findings provide insights into overcoming radiation-induced degradation and malfunction in semiconductor integrated circuits, which is particularly relevant for advancing space, nuclear, and defense industries.

Space-based search coil (SC) magnetometers connected to preamplifiers have been used to investigate magnetic field vectors of plasma waves from 100 mHz to 10 kHz for understanding magnetospheric dynamics. However, flicker noise below several 100 Hz of typical preamplifiers degrades the noise equivalent magnetic induction (NEMI) of SCs and affects the probing of plasma waves from 100 mHz to 100 Hz. In this study, we developed a chopper-stabilized preamplifier using application-specific integrated circuit (ASIC) technology for improving the NEMI below 100 Hz while maintaining miniaturization and a low power consumption. The chopper ASIC preamplifier fits into a layout size of 2.3 × 3.4 mm in a bare chip. We used two SC sensors with different (20 cm and 5 cm) lengths to evaluate the NEMI with the prototype of the chopper ASIC preamplifier. At 100 mHz, the NEMI values of the 20-cm length and 5-cm length SCs were 0.1 nT/Hz1/2 and 1.9 nT/Hz1/2, respectively, which can detect typical electromagnetic ion cyclotron waves in the magnetosphere. The NEMI value at 100 mHz for the 5-cm-length SC was improved by approximately 19 dB compared with that for a previous ASIC preamplifier without chopping. We conducted temperature tests for the chopper ASIC preamplifier to evaluate the behavior for under a wide temperature range from − 40 to + 100 °C. The temperature coefficient of the gain was approximately − 0.02 dB/°C, which is a sufficiently low temperature-dependence. The use of ASIC technology achieved high stability under the wide temperature range and radiation tolerance. Thus, the chopper ASIC preamplifier with high robustness and ultra-low noise characteristics is suitable for plasma wave observations in harsh space environments for future missions.

With the exponential growth of the Internet of Things (IoT), ensuring robust end-to-end encryption is paramount. Current cryptographic accelerators often struggle with balancing security, area efficiency, and power consumption, which are critical for compact IoT devices and system-on-chips (SoCs). This work presents a novel approach to designing substitution boxes (S-boxes) for Advanced Encryption Standard (AES) encryption, leveraging dual quad-bit structures to enhance cryptographic security and hardware efficiency. By utilizing Algebraic Normal Forms (ANFs) and Walsh–Hadamard Transforms, the proposed Register Transfer Level (RTL) circuitry ensures optimal non-linearity, low differential uniformity, and bijectiveness, making it a robust and efficient solution for ASIC implementations. Implemented on 65 nm CMOS technology, our design undergoes rigorous statistical analysis to validate its security strength, followed by hardware implementation and functional verification on a ZedBoard. Leveraging Cadence EDA tools, the ASIC implementation achieves a central circuit area of approximately 199 μm2. The design incurs a hardware cost of roughly 80 gate equivalents and exhibits a maximum path delay of 0.38 ns. Power dissipation is measured at approximately 28.622 μW with a supply voltage of 0.72 V. According to the ASIC implementation on the TSMC 65 nm process, the proposed design achieves the best area efficiency, approximately 66.46% better than state-of-the-art designs.

The Medium Energy X-ray telescope (ME) is one of the three main telescopes on board the Insight hard X-ray modulation telescope ( Insight- HXMT) astronomy satellite. ME contains 1728 pixels of Si-PIN detectors sensitive in 5–30 keV with a total geometrical area of 952 cm 2 . The application specific integrated circuit (ASIC) chip, VA32TA6, is used to achieve low power consumption and low readout noise. The collimators define three kinds of field of views (FOVs) for the telescope, 1°×4°, 4°×4°, and blocked ones. Combination of such FOVs can be used to estimate the in-orbit X-ray and particle background components. The energy resolution of ME is ~3 keV at 17.8 keV (FWHM) and the time resolution is 255 μs. In this paper, we introduce the design and performance of ME.

Deep neural networks (DNNs) have made significant achievements in a wide variety of domains. For the deep learning tasks, multiple excellent hardware platforms provide efficient solutions, including graphics processing units (GPUs), central processing units (CPUs), field programmable gate arrays (FPGAs), and application-specific integrated circuit (ASIC). Nonetheless, CPUs outperform other solutions including GPUs in many cases for the inference workload of DNNs with the support of various techniques, such as the high-performance libraries being the basic building blocks for DNNs. Thus, CPUs have been a preferred choice for DNN inference applications, particularly in the low-latency demand scenarios. However, the DNN inference efficiency remains a critical issue, especially when low latency is required under conditions with limited hardware resources, such as embedded systems. At the same time, the hardware features have not been fully exploited for DNNs and there is much room for improvement. To this end, this paper conducts a series of experiments to make a thorough study for the inference workload of prominent state-of-the-art DNN architectures on a single-instruction-multiple-data (SIMD) CPU platform, as well as with widely applicable scopes for multiple hardware platforms. The study goes into depth in DNNs: the CPU kernel-instruction level performance characteristics of DNNs including branches, branch prediction misses, cache misses, etc, and the underlying convolutional computing mechanism at the SIMD level; The thorough layer-wise time consumption details with potential time-cost bottlenecks; And the exhaustive dynamic activation sparsity with exact details on the redundancy of DNNs. The research provides researchers with comprehensive and insightful details, as well as crucial target areas for optimising and improving the efficiency of DNNs at both the hardware and software levels.

With the rapid growth in healthcare demand, an emergent, novel technology called wireless body area networks (WBANs) have become promising and have been widely used in the field of human health monitoring. A WBAN can collect human physical parameters through the medical sensors in or around the patient’s body to realize real-time continuous remote monitoring. Compared to other wireless transmission technologies, a WBAN has more stringent technical requirements and challenges in terms of power efficiency, security and privacy, quality of service and other specifications. In this paper, we review the recent WBAN medical applications, existing requirements and challenges and their solutions. We conducted a comprehensive investigation of WBANs, from the sensor technology for the collection to the wireless transmission technology for the transmission process, such as frequency bands, channel models, medium access control (MAC) and networking protocols. Then we reviewed its unique safety and energy consumption issues. In particular, an application-specific integrated circuit (ASIC)-based WBAN scheme is presented to improve its security and privacy and achieve ultra-low energy consumption.

A physical modeling approach was adopted to build a Digital Electro-Hydraulic Control (DEH) system simulation model and the fault models using the SIMULINK tool. This research combined the advantages of the gray system and neural network to build a multi-parameter gray error neural network fault prediction model for the first time. Furthermore, an embedded platform for intelligent fault diagnosis and prediction was developed using an Application Specific Integrated Circuit chip. The results show that the simulation model of the DEH system has good performance. A jam fault, internal leakage, and a device fault could be accurately identified through the fault diagnosis model. The multi-parameter gray error neural network prediction model improves the accuracy of fault prediction. The embedded platform developed by the Application Specific Integrated Circuit chip solves the problem of transmission limitation and insufficient computing power. It realizes the intelligent diagnosis and prediction of DEH system faults and guarantees the regular operation of the DEH system.

Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three‐clock cycle, divide‐and‐conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non‐idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re‐designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high‐security SM algorithm which involves random points to resist side‐channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state‐of‐the‐art designs reported in the literature in terms of speed and area‐time product metrics.

With the growing demand for secure image communication, effective encryption solutions are critical for safeguarding visual data from unauthorized access. The substitution box (S-box) in AES (Advanced Encryption Standard) is critical for ensuring nonlinearity and security. However, the static S-box used in AES is vulnerable to algebraic attacks, side-channel attacks, and so on. This study offers a novel Lorenz key and Chua key-based Reversible Substitution Box (LCK-SB) for image encryption, which takes advantage of the chaotic behavior of the Lorenz and Chua key systems to improve security due to nonlinear jumps and mixed chaotic behavior while maintaining optimal quantum cost, area, and power. The suggested method uses a hybrid Lorenz and Chua key generator to create a highly nonlinear and reversible S-box, which ensures strong confusion and diffusion features. The performance of the LCK-SB approach is examined on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms, and the findings show that quantum cost, delay, and power are decreased by 97%, 74.6%, and 35%, respectively. Furthermore, the formal security analysis shows that the suggested technique efficiently resists threats. The theoretical analysis and experimental assessment show that the suggested system is more secure for picture encryption, making it suitable for real-time and high-security applications.

High frame rate three-dimensional (3D) ultrasound imaging would offer excellent possibilities for the accurate assessment of carotid artery diseases. This calls for a matrix transducer with a large aperture and a vast number of elements. Such a matrix transducer should be interfaced with an application-specific integrated circuit (ASIC) for channel reduction. However, the fabrication of such a transducer integrated with one very large ASIC is very challenging and expensive. In this study, we develop a prototype matrix transducer mounted on top of multiple identical ASICs in a tiled configuration. The matrix was designed to have 7680 piezoelectric elements with a pitch of 300 μm × 150 μm integrated with an array of 8 × 1 tiled ASICs. The performance of the prototype is characterized by a series of measurements. The transducer exhibits a uniform behavior with the majority of the elements working within the −6 dB sensitivity range. In transmit, the individual elements show a center frequency of 7.5 MHz, a −6 dB bandwidth of 45%, and a transmit efficiency of 30 Pa/V at 200 mm. In receive, the dynamic range is 81 dB, and the minimum detectable pressure is 60 Pa per element. To demonstrate the imaging capabilities, we acquired 3D images using a commercial wire phantom.