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In addressing the issue of excessive high-frequency current ripple at the output port caused by high-frequency switching in traditional dual active bridge DC-DC converters, a low-ripple dual active bridge DC-DC converter was designed by replacing its switching devices with a half-bridge submodule. This converter constructs a decoupling loop for alternating and direct current components on the bridge arms, allowing the alternating components to form a loop between the bridge arms without entering the direct current port, thereby eliminating high-frequency current ripple at the direct current output port. Consequently, the filtering capacitors parallel to the direct current port can be omitted, while also suppressing direct current fault currents. Due to the inherent capacitance structure of the submodule switching devices, soft-switching characteristics are preserved, and conversion efficiency is not compromised. Simulation results based on a MATLAB/Simulink model of 750 V and 10 kW demonstrate that the ripple of this converter is less than 0.07%, a 90% reduction compared to traditional converters, and effectively suppresses fault currents, thereby enhancing system safety.

Modern measurement modules are extremely demanding on the hardware and must accurately capture the relevant parameters of capacitance and inductance. The inductance and its quality factor, capacitance and its loss angle tangent value are very important parameters, but also the current testing difficulties. To efficiently and accurately measure the inductance and its quality factor, capacitance and its loss angle tangent, this paper developed a capacitance-inductance testing method based on automatic balanced bridge circuit. Firstly, based on the DSP development board, test capacitance and inductance by switching dip switches; Then, the use of self-excited oscillation method to generate a fixed frequency sinusoidal signal, through the amplifier to increase the amplitude of its signal, and the use of adder to the signal to provide a certain bias to meet the amplitude requirements; Finally, based on the automatic balanced bridge method, through the full-wave rectification plus filter will be converted into the average of the signal to be tested, and then use the amplifier circuit to control the average value of the signal to be tested, and then use the amplifier circuit to control the average value. Then use the amplifier circuit to control the average value within the AD sampling range, and use the micro-controller to collect the test amplitude, phase and other related parameters. The test results show the effectiveness of the proposed method.

The converter station based on a half-bridge sub-module has poor tolerance to dc short-circuit faults, which puts forward higher requirements for the detection and breaking performance of dc circuit breakers (DCCBs). To this end, this paper proposes a Capacitance-Resistance hybrid fault current limiter (CRHCL) that can be integrated with DCCBs. The proposed CRHCL realizes the fast switching of the current limiting resistor through the thyristor and the pre-charged capacitor. The working principle and parameter configuration principle of CRHCL are described, and the theory and performance verification are carried out in the single-ended equivalent system simulation. The results show that compared with the traditional scheme of DCCB direct breaking, the proposal has a lower breaking current and breaking voltage, which effectively reduces the demand of DCCB for device number and breaking performance.

In the context of application in a power grid simulator, we investigated the parameter design issues of several crucial components of the Modular Multilevel Converter (MMC) topology applied to the power grid simulator system. These components include the bridge arm inductance and submodule capacitance. Based on the fundamental circuit of the MMC applied to the power grid simulator system, we introduced an equal discharge time constant H. We analyzed the capacitor voltage fluctuation rate and the equivalent capacitance discharge time constant “ H ”, discovering that they still exhibit an inversely proportional relationship across different engineering scenarios. Consequently, a general method for determining submodule capacitance parameters was proposed, and in conjunction with previous engineering parameters, recommended values for an equal discharge time constant of 40 ms were provided. Furthermore, we introduced the concepts of double-frequency circulating resonant angular frequency and phase resonant angular frequency, outlining the principles for determining the bridge arm reactance values. Through the analysis of corresponding parameters in previous engineering studies, universally applicable recommended values for the bridge arm reactance parameters were proposed, considering the unit resonant angular frequency as the power grid frequency angular frequency 1.0 ω .

In the single-phase two-stage AC/DC converter system, the inherent power fluctuation of double frequency will lead to the double frequency fluctuation of DC bus voltage, which will affect the stable operation of the converter. In addition, this fluctuation will also raise the current stress of the double active bridge. This makes it more difficult to design DC bus capacitance parameters. In this paper, a design method of DC bus capacitors based on high ripple operation is proposed, and the theoretical limit of DC bus voltage ripple is analyzed. On the premise of considering stable operation and current stress of converter, the capacitance of DC bus is reduced to improve the power density of the system. The design of capacitance parameters has a theoretical basis to follow. Finally, the correctness and effectiveness of the method are verified by examples.

This paper proposes a robust DC‐link voltage controller designed for a multilevel‐based static synchronous compensator (STATCOM), addressing both DC‐link capacitance degradation and load variations. The uncertainty in DC‐link capacitance is modeled as an external perturbation, leading to the development of a second‐order sliding mode controller (SOSMC) based on a twisting algorithm. This controller effectively manages these uncertainties, providing high stability and robustness against parameter variations and external disturbances. Furthermore, it reduces unwanted chattering and enhances overall system performance. The impact of DC‐link capacitance uncertainty on the reliability of multilevel converters is analyzed, comparing the proposed SOSMC with traditional proportional–integral (PI) controllers in the Simulink MATLAB environment. The results demonstrate that the SOSMC method outperforms the PI controller under 33% uncertainty in DC‐link capacitance over 5 years. The proposed control scheme not only meets reactive power demands but also effectively manages uncertainties in DC‐link capacitors. Additionally, the twisting algorithm maintains an acceptable total harmonic distortion (THD) index on the AC side, thereby improving overall reliability while reducing maintenance costs.

A NiCo2S4/N-CDs/RGO ternary composite hydrogel was prepared via a one-step hydrothermal method, utilizing lignin-based nitrogen-doped carbon dots as a bridge connecting NiCo2S4 and graphene. The specific capacitance of NiCo2S4/N-CDs/RGO significantly outperforms that of the GH and NiCo2S4/RGO electrodes, achieving 1050 F g−1. The 3D mesh porous hydrogel structure mitigates NiCo2S4 nanoparticle aggregation, providing a larger specific surface area for enhanced charge storage. The abundant functional groups of N-CDs interact with Ni (II) and Co (III) cations, favoring NiCo2S4 particle synthesis. Additionally, an assembled solid-state asymmetric supercapacitor employing NiCo2S4/N-CDs/RGO as the positive electrode exhibited excellent energy density (68.4 Wh kg−1) and cycle stability (82% capacitance retention after 10,000 constant current charge–discharge cycles).

The construction of p-NiO/n-Ga 2 O 3 heterojunction becomes a popular alternative to overcome the technological bottleneck of p-type Ga 2 O 3 for developing bipolar power devices for practical applications, whereas the identification of performance-limiting traps and the bipolar transport dynamics are still not exploited yet. To this end, the fundamental correlation of carrier transport, trapping and recombination kinetics in NiO/β-Ga 2 O 3 p + -n heterojunction power diodes has been investigated. The quantitative modeling of the temperature-dependent current-voltage characteristics indicates that the modified Shockley-Read-Hall recombination mediated by majority carrier trap states with an activation energy of 0.64 eV dominates the trap-assisted tunneling process in the forward subthreshold conduction regime, while the minority carrier diffusion with near-unity ideality factors is overwhelming at the bias over the turn-on voltage. The leakage mechanism at high reverse biases is governed by the Poole-Frenkel emissions through the β-Ga 2 O 3 bulk traps with a barrier height of 0.75 eV, which is supported by the identification of majority bulk traps with the energy level of E C − 0.75 eV through the isothermal capacitance transient spectroscopic analysis. These findings bridge the knowledge gap between bipolar charge transport and deep-level trap behaviors in Ga 2 O 3 , which is crucial to understand the reliability of Ga 2 O 3 bipolar power rectifiers.

Here, a gated‐anode diode (GAD) is proposed where an anode electrode is formed by connecting a gate electrode and an ohmic electrode of a normally‐off GaN HEMT for a 5.8 GHz rectenna. A wide recessed gate GaN GADs were prepared and the recess length dependence of their electrical characteristics was investigated. Typical DC characteristics of the HEMTs are a threshold voltage (Vth) of +0.3 V and a maximum drain current (Imax) of 300 mA/mm. The GADs showed the characteristics of maximum forward current (If) of 350 mA/mm, reverse breakdown voltage (BVr) of 40 V, and off‐state capacitance (Coff) of 0.28 pF/mm by using optimized recess length. We constructed SPICE model of the GADs. The SPICE simulation predicted a rectifier efficiency of 81% and a DC output power of 10 W for bridge type 5.8 GHz rectifier using four GADs with each gate width of 0.8 mm.

A fused silica dilatometer consisted of a rod and tube that had capacitance discs attached at one end. The cylindrical specimen of polycrystalline pure silicon 2.54 cm long and 0.635 cm in diameter was clamped between the other end of the rod and tube. These were enclosed in a fused silica furnace tube within the furnace. The furnace tube was sealed with helium that did not flow. The capacitance discs were sealed in a container outside of the furnace. Helium flowed within that container. These disks were used to measure the thermal expansion of pure silicon between 20 °C and 600 °C. The capacitance measurements were made by an Andean Hagerling capacitance bridge with a readout of ten digits and a sensitivity of 0.5 attofarads. The rate of heating and cooling was 1 °C·min −1 . The specimen temperature was measured using a calibrated platinum thermometer 3 mm away from the specimen. To correct for changes in disc expansion during a test, a silicon diode measured the temperature. Calibration of the capacitor extensometer was made using NIST fused silica and NIST stainless steel. The total thermal expansion of three silicon specimens measured between 20 °C and 600 °C was 2074.83 µstrain with a standard deviation of 17.43 µstrain. The hysteresis difference between the warming and cooling curves for the silicon was less than 7 µstrain.