Explore the vast range of titles available.

Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively. A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference.

A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field. This Perspective evaluates the state of the art in memristor-based electronics and explores the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing.

Disentangling the attributes of a sensory signal is central to sensory perception and cognition and hence is a critical task for future artificial intelligence systems. Here we present a compute engine capable of efficiently factorizing high-dimensional holographic representations of combinations of such attributes, by exploiting the computation-in-superposition capability of brain-inspired hyperdimensional computing, and the intrinsic stochasticity associated with analogue in-memory computing based on nanoscale memristive devices. Such an iterative in-memory factorizer is shown to solve at least five orders of magnitude larger problems that cannot be solved otherwise, as well as substantially lowering the computational time and space complexity. We present a large-scale experimental demonstration of the factorizer by employing two in-memory compute chips based on phase-change memristive devices. The dominant matrix–vector multiplication operations take a constant time, irrespective of the size of the matrix, thus reducing the computational time complexity to merely the number of iterations. Moreover, we experimentally demonstrate the ability to reliably and efficiently factorize visual perceptual representations. Sensory signal attributes can be disentangled exploiting the computation-in-superposition capability of hyperdimensional computing, in-memory computing and associated intrinsic device-level stochasticity.

Compute-in-memory based on resistive random-access memory has emerged as a promising technology for accelerating neural networks on edge devices. It can reduce frequent data transfers and improve energy efficiency. However, the nonvolatile nature of resistive memory raises concerns that stored weights can be easily extracted during computation. To address this challenge, we propose RePACK, a threefold data protection scheme that safeguards neural network input, weight, and structural information. It utilizes a bipartite-sort coding scheme to store data with a fully on-chip physical unclonable function. Experimental results demonstrate the effectiveness of increasing enumeration complexity to 5.77 × 10 75 for a 128-column compute-in-memory core. We further implement and evaluate a RePACK computing system on a 40 nm resistive memory compute-in-memory chip. This work represents a step towards developing safe, robust, and efficient edge neural network accelerators. It potentially serves as the hardware infrastructure for edge devices in federated learning or other systems. Emerging compute-in-memory technologies show potential in edge AI; however, information protection tools need further development. Here, authors propose an on-chip scheme to simultaneously protect neural network input, weight, and structural information with low circuit overhead.

A key challenge for deep neural network algorithms is their vulnerability to adversarial attacks. Inherently non-deterministic compute substrates, such as those based on analog in-memory computing, have been speculated to provide significant adversarial robustness when performing deep neural network inference. In this paper, we experimentally validate this conjecture for the first time on an analog in-memory computing chip based on phase change memory devices. We demonstrate higher adversarial robustness against different types of adversarial attacks when implementing an image classification network. Additional robustness is also observed when performing hardware-in-the-loop attacks, for which the attacker is assumed to have full access to the hardware. A careful study of the various noise sources indicate that a combination of stochastic noise sources (both recurrent and non-recurrent) are responsible for the adversarial robustness and that their type and magnitude disproportionately effects this property. Finally, it is demonstrated, via simulations, that when a much larger transformer network is used to implement a natural language processing task, additional robustness is still observed. Adversarial attacks threaten deep neural networks. Here, authors show analog in-memory computing chips enhance robustness, attributed to stochastic noise properties. This is validated experimentally and in simulations with larger transformer models.

In-memory computing chips based on magnetoresistive random-access memory devices can provide energy-efficient hardware for machine learning tasks.

Conductive bridging random access memory (CBRAM) has been considered to be a promising emerging device for artificial synapses in neuromorphic computing systems. Good analog synaptic behaviors, such as linear and symmetric synapse updates, are desirable to provide high learning accuracy. Although numerous efforts have been made to develop analog CBRAM for years, the stochastic and abrupt formation of conductive filaments hinders its adoption. In this study, we propose a novel approach to enhance the synaptic behavior of a SiNx/a-Si bilayer memristor through Ge implantation. The SiNx and a-Si layers serve as switching and internal current limiting layers, respectively. Ge implantation induces structural defects in the bulk and surface regions of the a-Si layer, enabling spatially uniform Ag migration and nanocluster formation in the upper SiNx layer and increasing the conductance of the a-Si layer. As a result, the analog synaptic behavior of the SiNx/a-Si bilayer memristor, such as the nonlinearity, on/off ratio, and retention time, is remarkably improved. An artificial neural network simulation shows that the neuromorphic system with the implanted SiNx/a-Si memristor provides a 91.3% learning accuracy mainly due to the improved linearity.Memory devices: Ionic implants help mimic the synapseAn approach that tweaks the structures of a new type of memory chip shows promise for neuromorphic computing applications. In conductive bridging random access memory (CBRAM) technology, nanoscale metal filaments inside special insulators are used to store data in either high or low conductance states. Inho Kim from the Korea Institute of Science and Technology in Seoul, South Korea and colleagues now report beneficial effects when germanium ions are implanted into silicon-based CBRAM using high-energy beams. The team’s microscopy experiments revealed that the implantation caused metal nanoclusters to distribute evenly within the device’s switching layer. These particles enabled smoother transitions between conductance states than conventional CBRAM, better mimicking the analog switching seen in synapses. Neural network simulations demonstrated that ion-implanted devices had significantly improved learning accuracy compared to unmodified CBRAM chips.

In NAND flash storage devices, the random access memory (RAM) is composed of a data buffer and mapping cache that play critical roles in storage performance. Furthermore, as the capacity growth rate of RAM chips lags far behind that of flash memory chips, determining how to take advantage of precious RAM is still a crucial issue. However, most existing buffer management studies on storage devices report performance degradation since these devices cannot refine reference regularities such as sequential, hot, or looping data patterns. In addition, most of these studies focus only on separately managing the data buffer or mapping cache. Compared with the existing buffer/cache management schemes (BMSs), we propose a unified RAM management (URM) scheme for not only the mapping cache but also the data buffer in NAND flash storage devices. URM compresses the mapping table to save memory space, and the remaining dynamic RAM space is used for the data buffer. For the data buffer part, we utilize the program counter-technique in the host layer that provides automatic pattern recognition for different applications, in contrast to existing BMSs. The program counter-technique in our design is able to distinguish four patterns. According to these patterns, the data buffer is divided into four size-adjustable zones. Therefore, our approach is linked to multimodal data and used in a data-intensive system. In particular, in URM, we use a multivariate classification to predict prefetching length in mapping buffer management. Our multivariate classification is transformed into multiple binary classifications (logistic regressions). Finally, we extensively evaluate URM using various realistic workloads, and the experimental results show that, compared with three data buffer management schemes, CFLRU, BPLRU, and VBBMS, URM can improve the hit ratio of data buffer and save response time by an average to 32% and 18%, respectively.

Recently, embedded devices are playing a prominent role in digital signal processors, multi-core systems, and hybrid processors. The performance of embedded devices is purely dependent on the memory allocation operations. However, the conventional memory allocators failed to improve the speed requirements by reducing the area, delay, and power metrics. Therefore, this article is focused on the development of a data management engine-based network on chip (DME-NoC) processor, which improves the performance by adopting the parallel memory allocation (PMA) controller

Electronic and photonic technologies have transformed our lives—from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1 , 2 . This goal is hindered by the fact that most silicon nanotechnologies—which enable our processors, computer memory, communications chips and image sensors—rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal–oxide–semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3 , 4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of ‘systems on a chip’ 1 , 6 – 8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10 , 11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics. A way of integrating photonics with silicon nanoelectronics is described, using polycrystalline silicon on glass islands alongside transistors on bulk silicon complementary metal–oxide–semiconductor chips.