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In this work, we design and simulate carbon nanotube field effect transistor (CNTFET) based open-loop and dynamic comparators and compared the performance with complementary metal oxide semiconductor (CMOS) based open loop and dynamic comparators. Four types of comparators have been designed; a two-stage comparators, a push–pull output comparators, dynamic comparators and double-tail dynamic comparator (DTDC), employing 32 nm technology node using CNTFETs and the conventional MOSFETs. A comparative analysis of key performance measuring parameters such as output voltage, rise time, fall time, duty cycle, average power and slew rate and area etc. have been done. The simulation studies have shown that the CNTFET based comparators consumes lesser power by 3 orders, results in higher speed and gives output close to their supply rails in comparison to CMOS based comparators. Further, effects of variation in temperature on frequency and power have been thoroughly studied. Simulation results show that CNTFET based comparators gives insensitive behavior for variation in temperature. All the proposed circuits are fully integrable because of the use of active components in the circuits.

This paper presents a proposed inverter‐based triple‐tail comparator designed for high‐speed and high‐efficiency applications in analogue‐to‐digital converters. In this proposed comparator, auxiliary inverter based pre‐amplifier is proposed to maintain the gain of the pre‐amplification stage and bolstering the robustness of the pre‐amplifier. Combined with offset cancelled technique, the definite state for each prior to comparison eliminates hysteresis effects. Utilizing the 28 nm CMOS process, the comparator achieves a high‐speed data conversion rate of 2 GHz and a root mean square offset of 1.5 mV, representing a reduction of over 62% compared to traditional structures. In this proposed comparator, auxiliary inverter based pre‐amplifier is proposed to maintain the gain of the pre‐amplification stage and bolstering the robustness of the pre‐amplifier. Combined with offset cancelled technique, the definite state for each prior to comparison eliminates hysteresis effects.

Existing conformal prediction methods for time-to-event outcomes leverage only baseline covariates, producing prediction intervals that are insufficiently informative to facilitate decision making. We propose History-Aware Prediction Sets (HAPS), a conformal framework that constructs prediction sets for individual event times using covariate histories observed up to a decision time, targeting coverage among individuals who have survived to this time. HAPS handles right censoring adjusted for time-varying confounders via inverse probability of censoring weighting. When the censoring weights are consistently estimated, it achieves PAAC (probably asymptotically approximately correct) coverage among survivors. We further propose two doubly robust extensions of HAPS to weaken reliance on consistent estimation of the censoring distribution. In simulations, HAPS and its extensions reduce median prediction interval length by up to 75\\% relative to baseline comparators while maintaining close to nominal coverage. On two public benchmark data sets, HAPS reduces the median interval length by up to 60\\% for predictions at year 5, compared to the baseline comparators.

Omniprediction is a learning problem that requires suboptimality bounds for each of a family of losses \\(L\\) against a family of comparator predictors \\(C\\). We initiate the study of omniprediction in a multiclass setting, where the comparator family \\(C\\) may be infinite. Our main result is an extension of the recent binary omniprediction algorithm of [OKK25] to the multiclass setting, with sample complexity (in statistical settings) or regret horizon (in online settings) \\( ^-(k+1)\\), for \\(\\)-omniprediction in a \\(k\\)-class prediction problem. En route to proving this result, we design a framework of potential broader interest for solving Blackwell approachability problems where multiple sets must simultaneously be approached via coupled actions.

Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit’s overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance.

The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high‐order systems. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × passive gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs.

A comparator circuit applied to a 12-bit successive approximation analog-to-digital converter (SAR ADC) is proposed in this paper. The circuit is designed based on 0.18 μm CMOS technology, consisting of an open-loop comparator, a regenerative comparator, and buffer circuits. The open-loop comparator adopts a differential input structure and incorporates cross-coupled pairs to enhance gain, introducing reset and clamping techniques to improve speed. The regenerative comparator employs a positive feedback structure to enhance response speed. Additionally, a novel biasing circuit using external components for fine-tuning is designed to address performance degradation caused by process variations in bias current, thereby improving the stability of the comparator circuit, which can serve as an analog IP core for SAR ADC design. Simulation verification is conducted by using a Cadence Spectre simulator with a working voltage of 3.3 V and a sampling frequency of 3.2 MHz. Simulation results indicate that the comparator achieves a resolution of 0.4 mV, with an accuracy of 12 bits and a dynamic power consumption of 1.8 mW. The proposed circuit has been successfully applied in 12-bit SAR ADC.

Accuracy is an important index in the design of clock circuits. The clock performance is affected by the fact that the delay time of the comparator in the circuit is strongly influenced by the temperature. This paper presents a principal analysis of this phenomenon and proposes a specific method for optimizing clock accuracy. By changing the comparator’s reference voltage, the clock accuracy is improved to meet the high-precision clock requirements. The high-precision clock frequency designed in this paper is 24 MHz, with temperature stability of ±1%.

Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC's like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.