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In this work, we design and simulate carbon nanotube field effect transistor (CNTFET) based open-loop and dynamic comparators and compared the performance with complementary metal oxide semiconductor (CMOS) based open loop and dynamic comparators. Four types of comparators have been designed; a two-stage comparators, a push–pull output comparators, dynamic comparators and double-tail dynamic comparator (DTDC), employing 32 nm technology node using CNTFETs and the conventional MOSFETs. A comparative analysis of key performance measuring parameters such as output voltage, rise time, fall time, duty cycle, average power and slew rate and area etc. have been done. The simulation studies have shown that the CNTFET based comparators consumes lesser power by 3 orders, results in higher speed and gives output close to their supply rails in comparison to CMOS based comparators. Further, effects of variation in temperature on frequency and power have been thoroughly studied. Simulation results show that CNTFET based comparators gives insensitive behavior for variation in temperature. All the proposed circuits are fully integrable because of the use of active components in the circuits.

The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high‐order systems. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs. This work proposes a new fully passive NS‐SAR technique, it can realize 2 × passive gain with a simple structure, leading to the reduced comparator power, and less parasitics. This technique is also easy to extend to high‐order NS‐SAR ADCs.

A comparator circuit applied to a 12-bit successive approximation analog-to-digital converter (SAR ADC) is proposed in this paper. The circuit is designed based on 0.18 μm CMOS technology, consisting of an open-loop comparator, a regenerative comparator, and buffer circuits. The open-loop comparator adopts a differential input structure and incorporates cross-coupled pairs to enhance gain, introducing reset and clamping techniques to improve speed. The regenerative comparator employs a positive feedback structure to enhance response speed. Additionally, a novel biasing circuit using external components for fine-tuning is designed to address performance degradation caused by process variations in bias current, thereby improving the stability of the comparator circuit, which can serve as an analog IP core for SAR ADC design. Simulation verification is conducted by using a Cadence Spectre simulator with a working voltage of 3.3 V and a sampling frequency of 3.2 MHz. Simulation results indicate that the comparator achieves a resolution of 0.4 mV, with an accuracy of 12 bits and a dynamic power consumption of 1.8 mW. The proposed circuit has been successfully applied in 12-bit SAR ADC.

Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit’s overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance.

Accuracy is an important index in the design of clock circuits. The clock performance is affected by the fact that the delay time of the comparator in the circuit is strongly influenced by the temperature. This paper presents a principal analysis of this phenomenon and proposes a specific method for optimizing clock accuracy. By changing the comparator’s reference voltage, the clock accuracy is improved to meet the high-precision clock requirements. The high-precision clock frequency designed in this paper is 24 MHz, with temperature stability of ±1%.

Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC's like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.

This paper presents the design of multiplexer-based Flash ADC with a reduced number of comparators to achieve less area and less power consumption with increased resolution. As the number of bits increases, flash ADC needs a huge number of comparators which increases the area of the chip, and also the power consumption will increase. The conventional N-Bit Flash ADC requires a 2N number of resistors and 2N-1 number of preamplifiers and comparators. Here the number of comparators is reduced by using multiplexers by providing reference voltage through multiplexers. And also, the encoder is designed using multiplexers. The 6-bit Flash ADC is designed utilizing multiplexers and a reduced number of comparators. The Simulation is done by using the proteus 8.9 design suite with 1v supply voltage.

This paper presents a proposed inverter‐based triple‐tail comparator designed for high‐speed and high‐efficiency applications in analogue‐to‐digital converters. In this proposed comparator, auxiliary inverter based pre‐amplifier is proposed to maintain the gain of the pre‐amplification stage and bolstering the robustness of the pre‐amplifier. Combined with offset cancelled technique, the definite state for each prior to comparison eliminates hysteresis effects. Utilizing the 28 nm CMOS process, the comparator achieves a high‐speed data conversion rate of 2 GHz and a root mean square offset of 1.5 mV, representing a reduction of over 62% compared to traditional structures. In this proposed comparator, auxiliary inverter based pre‐amplifier is proposed to maintain the gain of the pre‐amplification stage and bolstering the robustness of the pre‐amplifier. Combined with offset cancelled technique, the definite state for each prior to comparison eliminates hysteresis effects.

Introduction: Increasing evidence highlights the allergenic potential of pegylated drugs as a result of the production of anti-PEG immunoglobulins [1-3]. Objective: To investigate the risk of hypersensitivity reactions of pegylated drugs using the Italian spontaneous adverse drug reaction (ADR) reporting system database (SRS). Methods: We selected ADR reports attributed to medicinal products containing pegylated active substances and/or pegylated liposomes from the Italian SRS in the period between its inception and March 2021. As comparators, we extracted ADR reports of medicinal products containing the same non-pegylated active substances and/or non-pegylated liposomes (if not available, compounds belonging to the same mechanistic class). A descriptive analysis of all ADR reports, and of hypersensitivity reactions specifically, was carried out. Reporting rates and time to onset of hypersensitivity reactions for each medicinal product were also calculated. As a measure of hypersensitivity reactions reporting disproportionality, we also calculated the reporting odds ratio. Furthermore, the relationship between the proportion of hypersensitivity reactions for the study drugs and their PEG size was assessed. Results: Overall, 3,865 ADR reports were related to pegylated medicinal products and 11,961 to their non-pegylated comparators. Concerning both overall ADRs and hypersensitivity reactions reports, around two-thirds of patients were females and they mostly concerned patients aged between 46 and 64 years. The frequency of hypersensitivity reactions reporting was higher among pegylated vs. nonpegylated medicinal products (11.7% vs. 9.4%, p < 0.0001) and the proportion of serious hypersensitivity reactions was two times higher for pegylated vs. non-pegylated medicinal products (33.0% vs. 16.3%; p < 0.0001). The hypersensitivity reaction reporting rates were always higher for pegylated vs. non-pegylated medicinal products, with reporting rate ratios ranging from 1.4 (95% CI 0.8-2.5) for pegfilgrastim vs. filgrastim to 20.0 (95% CI 2.8-143.5) for peginterferon alpha-2a vs. interferon alpha-2a. The median time to onset of hypersensitivity reactions ranged from < 1 day and 69 days for pegylated medicinal products, and from < 1 day and 345 days for non-pegylated comparators. Disproportionality analysis showed that both pegylated and non-pegylated medicinal products were not associated with an increased reporting trend of hypersensitivity reactions. Moreover, higher PEG molecular weights were not statistically associated with an increased risk of hypersensitivity reaction reporting. Conclusion: Although disproportionality analysis showed that neither pegylated nor non-pegylated medicinal products were associated with an increased hypersensitivity reactions reporting trend, findings of this study suggest a potential involvement for pegylation in triggering drug-related hypersensitivity reactions, especially clinically relevant ones. However, further clinical assessment is required to validate pharmacovigilance data.