Journal Article

A high precision comparator design for 12-bit SAR ADC

Fu, Yikun, Li, Haisong, Jiang, Yihu

2024

Overview

A comparator circuit applied to a 12-bit successive approximation analog-to-digital converter (SAR ADC) is proposed in this paper. The circuit is designed based on 0.18 μm CMOS technology, consisting of an open-loop comparator, a regenerative comparator, and buffer circuits. The open-loop comparator adopts a differential input structure and incorporates cross-coupled pairs to enhance gain, introducing reset and clamping techniques to improve speed. The regenerative comparator employs a positive feedback structure to enhance response speed. Additionally, a novel biasing circuit using external components for fine-tuning is designed to address performance degradation caused by process variations in bias current, thereby improving the stability of the comparator circuit, which can serve as an analog IP core for SAR ADC design. Simulation verification is conducted by using a Cadence Spectre simulator with a working voltage of 3.3 V and a sampling frequency of 3.2 MHz. Simulation results indicate that the comparator achieves a resolution of 0.4 mV, with an accuracy of 12 bits and a dynamic power consumption of 1.8 mW. The proposed circuit has been successfully applied in 12-bit SAR ADC.

• Publisher: IOP Publishing
• Subject: Analog circuits / Analog to digital converters / Comparator circuits / Comparators / Design / Performance degradation / Positive feedback