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The rapid advancements in the field of autonomous systems have led to a significant demand for artificial‐intelligence‐of‐things (AIoT) edge‐compatible neuromorphic training accelerators with continual/online learning capability. These accelerators require a large network of synaptic elements with high degree of plasticity, high endurance, large integration density, and ultralow programing energy. Although emerging nonvolatile memories exhibit promising potential as synaptic devices, their widespread application in training accelerators is limited due to their low endurance and immature fabrication technology. In contrast, capacitor‐less 1 transistor‐dynamic random‐access memories (1T‐DRAMs) have recently emerged as lucrative alternative to the conventional (1T/1C) DRAMs owing to their high scalability and low footprint. Considering the high endurance, large integration density, and ultralow write energy of the 1T‐DRAMs, in this work, for the first time, their potential is explored as synaptic elements for online learning. The proposed 1T‐DRAM‐based synaptic element exhibits multi‐level capability (up to 6 bits), a large dynamic range (3.91 × 103), an ultralow energy, and an appreciable linearity for potentiation/depression. The 1T‐DRAM‐based synaptic element also exhibits a paired pulse facilitation with an exponential decay similar to the biological synapses. Furthermore, a multilayer perceptron utilizing the proposed 1T‐DRAM synapses achieves an accuracy of 87.10% on MNIST dataset. This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge‐compatible neuromorphic training accelerators with continual/online learning capability.

This study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs. By leveraging the floating body effect, this architecture eliminates the need for capacitors, thereby improving integration density and memory performance. Through Sentaurus technology computer-aided design simulations, we compare the PE NS 1T-DRAM device with a conventional NS 1T-DRAM device to evaluate its effectiveness. The results reveal superior retention time (RT) and sensing margin (SM) performance of the proposed PE NS 1T-DRAM device, surpassing the memory criteria outlined by the International Roadmap for Devices and Systems, which requires an RT exceeding 64 ms at 358 K. This enhanced performance of the proposed device is attributed to its extension region, which functions as a potential well for efficient hole storage, as well as the suppression of Shockley‒Read‒Hall recombination. The PE NS 1T-DRAM device also demonstrates robustness to disturbances, maintaining over 89% of its SM and RT under diverse conditions. This superiority is again attributed to its extension region, which minimizes the effects of current flow and electrostatic potential rise. These results highlight the potential of the PE NS 1T-DRAM design for future high-density memory applications.

This study examines the influence of cell capacitance on data retention characteristics in dynamic random access memory (DRAM) cells composed of two transistors, in short, 2‐transistor (2T) DRAM. The 2T DRAM is gaining attention not only as a standalone memory technology but also as a critical component for processing‐in‐memory (PIM) applications, offering the full compatibility with standard Si processing. The 2T configuration employs separate transistors for write and read operations, enabling flexible bit‐cell design and efficient parallel processing in PIM architectures. However, the small storage node (SN) capacitance, especially when the cell capacitor is truncated, poses challenges for data retention. This work presents a design methodology to enhance data retention in 2T DRAM cells by optimizing transistor dimensions and biasing schemes. Circuit simulations using the 180 nm standard process show that the proposed approach improves retention time by 35% and reduces leakage current by 22% compared to baseline designs. Furthermore, the write transistor current demonstrates a 15% improvement in stability during repeated read operations within the retention time. These results highlight the potential of the proposed design to mitigate retention‐related issues and enhance computational accuracy in PIM applications.

In this study, we designed and analyzed a single-transistor dynamic random-access memory (1 T-DRAM) based on an arch-shaped gate-all-around tunnel field-effect transistor (GAA ARCH-TFET), featuring an Si/SiGe heterostructure, for high-density memory applications. Unlike conventional 1 T-DRAM, which relies on the electric-field-driven movement of charge carriers through a channel for the read operation, the GAA ARCH-TFET 1 T-DRAM utilizes band-to-band tunneling. The GAA structure improves scalability, making it suitable for high-density memory applications. This capacitorless GAA ARCH-TFET 1 T-DRAM cell demonstrates both superior performance and low energy consumption. The arch-shaped design expands the tunneling area, while the Si/SiGe heterostructure forms a quantum well that further enhances memory performance. The effects of key parameters, including source height, channel height, and germanium composition, on device behavior are examined. Simulation results reveal that the GAA ARCH-TFET 1 T-DRAM achieves a high current ratio of read “1” to read “0” (108) and a retention time exceeding 1 s at 358 K. These characteristics suggest that the proposed device holds potential as a DRAM replacement in various applications.

Die-stacked dynamic random access memory (DRAM) caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main memory. To fully realize their potential, it is essential to improve DRAM cache hit rate and lower its cache hit latency. In order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time, we propose a partial direct-mapped die-stacked DRAM cache called P3DC. This design is motivated by a key observation, i.e., applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency simultaneously. To address this problem, P3DC classifies data blocks into leading blocks and following blocks, and places them at static positions and dynamic positions, respectively, in a unified set-associative structure. We also propose a replacement policy to balance the miss penalty and the temporal locality of different blocks. In addition, P3DC provides a policy to mitigate cache thrashing due to block type variations. Experimental results demonstrate that P3DC can reduce the cache hit latency by 20.5% while achieving a similar cache hit rate compared with typical set-associative caches. P3DC improves the instructions per cycle (IPC) by up to 66% (12% on average) compared with the state-of-the-art direct-mapped cache—BEAR, and by up to 19% (6% on average) compared with the tag-data decoupled set-associative cache—DEC-A8.

The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean operations directly within the 2T DRAM array, thereby minimizing data movement between the CPU and DRAM and effectively alleviating the bottleneck. The 2T DRAM array was implemented using the mixed-mode simulation capability of SILVACO TCAD, and its read, write, and hold operations were successfully verified. Building on this foundation, OR and AND logic operations were realized by modulating the gate voltages of MOSFETs within the 2T DRAM array. To enable XNOR functionality, an auxiliary circuit consisting of three additional MOSFETs was integrated. Furthermore, as the ultimate goal of PIM is to enable memory to perform computational tasks, support for MAC operations becomes essential. To facilitate this, we designed a refresh circuit capable of maintaining multi-state data, which is critical for MAC operations. This circuit, also composed of three MOSFETs, functions as a key component for multi-state data retention within the 2T DRAM array. In summary, we demonstrate the implementation of Boolean logic operations using the 2T DRAM array and a three-MOSFET auxiliary circuit and propose a compact refresh circuit to support MAC operations, advancing the potential of PIM architectures.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

Wide‐bandgap (WBG) semiconductors are at the forefront of driving innovations in electronic technology, perpetuating Moore's Law and opening up new avenues for electronic devices. Although β‐Ga2O3 has attracted extensive research interest in advanced electronics, its high‐temperature and high‐speed volatile memory applications in harsh environment has been largely overlooked. Herein, a high‐performance hexagonal boron nitride (h‐BN)/β‐Ga2O3 heterostructure junction field‐effect transistor (HJFET) is fabricated, exhibiting an off‐state current as low as ≈10 fA, a high on/off current ratio of ≈108, a low contact resistance of 5.6 Ω·mm, and an impressive field‐effect electron mobility of 156 cm2  （Vs）−1. Notably, the current h‐BN/β‐Ga2O3 HJFET exhibits outstanding thermal reliability in the ultra‐wide temperature range from 223 to 573 K, as well as long‐term environmental stability in air, which confirms its inherent capability of operation in harsh environments. Moreover, the h‐BN/β‐Ga2O3 HJFET demonstrates successful applications for accelerator‐in‐memory computing fields, including dynamic random‐access memory structure and neural network computations. These superior characteristics position β‐Ga₂O₃‐based electronics as highly promising for applications in extreme environments, with particular relevance to the automotive, aerospace, and sensor sectors. The h‐BN/β‐Ga2O3 heterostructure junction field‐effect transistor with exceptional stability, featuring a high on/off current ratio of ~108 and an impressive field‐effect electron mobility of 156 cm2/Vs.

Dynamic random-access memory (DRAM) is crucial for high-performance computing due to its speed and storage capacity. As the demand for high-capacity memory increases, DRAM has adopted a scaled-down approach for the next generation. However, the reduced distance between cells leads to electrical interference, known as the 1-row Hammer effect, which degrades DRAM performance and poses security risks. Therefore, the 1-row Hammer effect is a critical issue in current DRAM technology. In this study, we investigate the principles and impact of the 1-row Hammer phenomenon on DRAM. The 1-row Hammer effect can cause two types of failures: D0 and D1. We focus on D0 failures, which occur when stored data transition from 0 to 1 due to repeated accesses. This phenomenon involves the capture and diffusion of electrons, influenced by interfacial traps and device structures. To investigate the D0 failure, we simulated the 1-row Hammer effect using a mixed-mode approach to examine its effects on interfacial traps and device structure changes. This study aims to improve our understanding of row Hammer and suggests a mitigation strategy using buried oxide. The proposed structure mitigates the D0 failure by approximately 25%, effectively improving the security and reliability of DRAM.

As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlenecks in AI systems, and processing-in-memory (PIM) architectures have been proposed to overcome this issue. PIM is an architecture that performs computations within memory, thereby reducing data movement between the CPU and memory. However, since PIM is difficult to optimize as a general-purpose architecture, it is essential to adopt an architecture suitable for the target application. While various simulators and emulators have been introduced for the design space exploration (DSE) of different PIM architectures, simulators are limited in debugging hardware operations, and emulators face challenges in flexibly modifying the system configuration, as emulators implement the entire architecture in hardware. Therefore, this paper introduces PIMCoSim, a comprehensive hardware–software co-simulator for the DSE of DRAM-PIM systems. This co-simulator partially emulates simplified hardware-implemented processing elements (PEs) and integrates software models for memory operations, facilitating the DSE of PIM systems. To validate PIMCoSim, we analyzed results for different computational workloads by varying PIM structures and operational policies, demonstrating the efficiency of DRAM-PIM systems. The co-simulation approach in PIMCoSim aims to contribute to analyzing DRAM-PIM configurations and adopting optimized structures.