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Large-scale electromagnetic transient simulation of power systems in real-time using detailed modelling is computationally very demanding. This study introduces a multi-field programmable gate array (FPGA) hardware design for this purpose. A functional decomposition method is proposed to map FPGA hardware resources to system modelling. This systematic method lends itself to fully pipelined and parallel hardware emulation of individual component models and numerical solvers, while preserving original system characteristics without the need for extraneous components to partition the system. Proof-of-concept is provided in terms of a 3-FPGA and 10-FPGA real-time hardware emulation of a three-phase 42-bus and 420-bus power systems using detailed modelling of various system components and iterative non-linear solution on a 100 MHz FPGA clock. Real-time results are compared with offline simulation results, and conclusions are derived on the performance and scalability of this multi-FPGA hardware design.

A new generation of aperture synthesis passive millimetre‐wave imager is being developed for security screening using 4096 element antennas with 3.5 GHz bandwidth, enabling high radiometric sensitivity at a video frame rate. This paper proposed a high performance digital correlator deployed in such system that uses integrated connectors to input a 1 GHz bandwidth, 32 I/Q input signals from IF processors. The proposed correlator is implemented up to 2080 of 2‐bit/4‐level (2B/4L) correlation units in a field programmable gate array (FPGA). A novel structure suitable for an FPGA is developed, occupying less than 11% of hardware resource utilisation, allowing a maximum clock frequency of over 289 MHz. A test system is built to verify the design, and a correlation efficiency above 99.4% is observed at the proposed interval, which outperforms other state‐of‐the‐art zero‐lag digital cross‐correlators. We introduce a novel 1 GHz 64‐channel digital correlator with 2B/4L quantisation circuit design based on field programmable gate array (FPGA). The overall design makes full use of hardware resources, aiming for high radiometric sensitivity through the integration of massive correlation units.

Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques and digital signatures have been applied to protect and authenticate relevant information. However, with the advent of quantum computers and quantum algorithms, classical cryptographic techniques have been in danger of collapsing because quantum computers can solve complex problems in polynomial time. Stemming from that risk, researchers worldwide have stepped up research on post-quantum algorithms to resist attack by quantum computers. In this review paper, we survey studies in recent years on post-quantum cryptography (PQC) and provide statistics on the number and content of publications, including a literature overview, detailed explanations of the most common methods so far, current implementation status, implementation comparisons, and discussion on future work. These studies focused on essential public cryptography techniques and digital signature schemes, and the US National Institute of Standards and Technology (NIST) launched a competition to select the best candidate for the expected standard. Recent studies have practically implemented the public key encryption/key encapsulation mechanism (PKE/KEM) and digital signature schemes on different hardware platforms and applied various optimization measures based on other criteria. Along with the increasing number of scientific publications, the recent trend of PQC research is increasingly evident and is the general trend in the cryptography industry. The movement opens up a promising avenue for researchers in public key cryptography and digital signatures, especially on algorithms selected by NIST.

In recent years, significant research and development efforts have been made to transform the Internet of Things (IoT) from a futuristic vision to reality. The IoT is expected to deliver huge economic benefits through improved infrastructure and productivity in almost all sectors. At the core of the IoT are the distributed sensing devices or sensor nodes that collect and communicate information about physical entities in the environment. These sensing platforms have traditionally been developed around off-the-shelf microcontrollers. Field-Programmable Gate Arrays (FPGA) have been used in some of the recent sensor nodes due to their inherent flexibility and high processing capability. FPGAs can be exploited to huge advantage because the sensor nodes can be configured to adapt their functionality and performance to changing requirements. In this paper, FlexiS, a high performance and flexible sensor node platform based on FPGA, is presented. Test results show that FlexiS is suitable for data and computation intensive applications in wireless sensor networks because it offers high performance with low energy profile, easy integration of multiple types of sensors, and flexibility. This type of sensing platforms will therefore be suitable for the distributed data analysis and decision-making capabilities the emerging IoT applications require.

Attacks on Internet of Things (IoT) devices are on the rise. Physical Unclonable Functions (PUFs) are proposed as a robust and lightweight solution to secure IoT devices. The main advantage of a PUF compared to the current classical cryptographic solutions is its compatibility with IoT devices with limited computational resources. In this paper, we investigate the maturity of this technology and the challenges toward PUF utilization in IoT that still need to be addressed.

The article explores the application of digital circuits, such as logic gates, logic functions, flip-flop, and automata, using the Nexys 4 DDR platform from Xilinx and the Vivado software. The Nexys 4 DDR, featuring the Artix-7 FPGA, provides a robust environment for designing and testing digital systems. It allows for efficient implementation of various digital functions through hardware programming and simulation. The use of Vivado software eases the creation, simulation, and deployment of custom digital circuits, highlighting the versatility and power of FPGA technology in real-world applications. This paper highlights key principles, practical implementations, and design considerations involved in using these tools for digital circuit applications.

Prototyping using multi-FPGA platforms is unique because of its use in real-world testing and cycle-accurate information on the design. However, this is a complex and time-consuming process with multiple sub-steps. Among its sub-steps, inter-FPGA routing is the one that can take a significant percentage of total prototyping time. The share of inter-FPGA routing is projected to increase further over time with the ever-increasing complexity of the target designs. In this work, we propose to integrate a Reinforcement Learning (RL)-based framework to speed up the inter-FPGA routing process. For this purpose, we first find a trade-off between the exploration and exploitation approach (also termed as the ϵ-greedy approach) in our RL-based framework while not affecting the final Quality of Results (QoR). To gauge its effectiveness, we then perform an extensive comparison between the proposed framework and established routing approaches. In this regard, a set of fourteen complex benchmarks is used, and the results of the proposed framework are compared against existing routability- and timing-driven routing approaches. Experimental results reveal that, on average, the proposed RL-based framework speeds up the inter-FPGA routing process by 45% and 32%, compared to routability- and timing-driven routing approaches, respectively. The speedup at the routing step further leads to an overall speedup of the backend flow by 22% and 15%, respectively.

This proposed research explores a novel approach to image classification by deploying a complex-valued neural network (CVNN) on a Field-Programmable Gate Array (FPGA), specifically for classifying 2D images transformed into polar form. The aim of this research is to address the limitations of existing neural network models in terms of energy and resource efficiency, by exploring the potential of FPGA-based hardware acceleration in conjunction with advanced neural network architectures like CVNNs. The methodological innovation of this research lies in the Cartesian to polar transformation of 2D images, effectively reducing the input data volume required for neural network processing. Subsequent efforts focused on constructing a CVNN model optimized for FPGA implementation, emphasizing the enhancement of computational efficiency and overall performance. The experimental findings provide empirical evidence supporting the efficacy of the image classification system developed in this study. One of the developed models, CVNN_128, achieves an accuracy of 88.3% with an inference time of just 1.6 ms and a power consumption of 4.66 mW for the classification of the MNIST test dataset, which consists of 10,000 frames. While there is a slight concession in accuracy compared to recent FPGA implementations that achieve 94.43%, our model significantly excels in classification speed and power efficiency—surpassing existing models by more than a factor of 100. In conclusion, this paper demonstrates the substantial advantages of the FPGA implementation of CVNNs for image classification tasks, particularly in scenarios where speed, resource, and power consumption are critical.

Memristive neurons and memristive neural networks constructed based on memristors have important research significance for revealing the mystery of the brain. This paper proposes a compound hyperbolic tangent cubic nonlinear memristor, which has nonvolatile memory characteristics and local activity characteristics. In particular, the memristor also has three stable pinched hysteresis loops under different initial values. The memristor is applied to Fitzhugh–Nagumo neuron and Hindmarsh–Rose neuron to establish five different memristive neural models, and a series of firing dynamics analysis are carried out on them. At the same time, we not only discuss multiple firing patterns on a single memristive neuron and double memristive coupled neurons, but also compare which neuron and which coupled neural network the proposed memristor is more suitable for, which is a lack of comprehensive investigation in the published research. Furthermore, digital circuit experiment is performed on the FPGA development board to verify the firing mechanism of these memristive neural models, which has potential application value for some practical projects.