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In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating-point unit is developed. A least mean squares algorithm-based adaptive filter (LMS-AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS-AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74–100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non-invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2–7.51% in accuracy when compared to previous works.

The integrated electronic nose (e-nose) design, which integrates sensor arrays and recognition algorithms, has been widely used in different fields. However, the current integrated e-nose system usually suffers from the problem of low accuracy with simple algorithm structure and slow speed with complex algorithm structure. In this article, we propose a method for implementing a deep neural network for odor identification in a small-scale Field-Programmable Gate Array (FPGA). First, a lightweight odor identification with depthwise separable convolutional neural network (OI-DSCNN) is proposed to reduce parameters and accelerate hardware implementation performance. Next, the OI-DSCNN is implemented in a Zynq-7020 SoC chip based on the quantization method, namely, the saturation-flooring KL divergence scheme (SF-KL). The OI-DSCNN was conducted on the Chinese herbal medicine dataset, and simulation experiments and hardware implementation validate its effectiveness. These findings shed light on quick and accurate odor identification in the FPGA.

This proposed research explores a novel approach to image classification by deploying a complex-valued neural network (CVNN) on a Field-Programmable Gate Array (FPGA), specifically for classifying 2D images transformed into polar form. The aim of this research is to address the limitations of existing neural network models in terms of energy and resource efficiency, by exploring the potential of FPGA-based hardware acceleration in conjunction with advanced neural network architectures like CVNNs. The methodological innovation of this research lies in the Cartesian to polar transformation of 2D images, effectively reducing the input data volume required for neural network processing. Subsequent efforts focused on constructing a CVNN model optimized for FPGA implementation, emphasizing the enhancement of computational efficiency and overall performance. The experimental findings provide empirical evidence supporting the efficacy of the image classification system developed in this study. One of the developed models, CVNN_128, achieves an accuracy of 88.3% with an inference time of just 1.6 ms and a power consumption of 4.66 mW for the classification of the MNIST test dataset, which consists of 10,000 frames. While there is a slight concession in accuracy compared to recent FPGA implementations that achieve 94.43%, our model significantly excels in classification speed and power efficiency—surpassing existing models by more than a factor of 100. In conclusion, this paper demonstrates the substantial advantages of the FPGA implementation of CVNNs for image classification tasks, particularly in scenarios where speed, resource, and power consumption are critical.

The study of no-equilibrium chaotic system is one of the recent hot topics. This paper constructs a new no-equilibrium chaotic system by introducing an additional variable and a constant term to a three-dimensional chaotic system. Different from the previous no-equilibrium chaotic system, the new system has period-doubling bifurcation and performs hidden chaotic attractors for a large constant term. The analog circuit and field-programmable gate array (FPGA) implementation are given to illustrate the existence of the system. By utilizing the new system, a chaotic magic cube transformation image encryption algorithm (CMCT-IEA) is proposed, which has a classical permutation-diffusion structure. A new permutation method is designed to scramble image pixels in three-dimensional space, and a diffusion method is developed to diffuse small pixel changes of the original image to all pixels in three-dimensional space. A dynamic key is also designed to improve the security of the encryption algorithm. We also analyze the security of CMCT-IEA in terms of computational complexity, statistical properties, and the ability to defend against several common attacks. Compared with several advanced algorithms, the CMCT-IEA exhibits excellent security characteristics.

This paper starts with a review of three-dimensional chaotic dynamical systems equipped with special curves of balance points. We also propose the mathematical model of a new three-dimensional chaotic system equipped with a closed butterfly-like curve of balance points. By performing a bifurcation study of the new system, we analyze intrinsic properties such as chaoticity, multi-stability, and transient chaos. Finally, we carry out a realization of the new multi-stable chaotic model using Field-Programmable Gate Array (FPGA).

Designing synthetic-aperture radar image formation systems can be challenging due to the numerous options of algorithms and devices that can be used. There are many SAR image formation algorithms, such as backprojection, matched-filter, polar format, Range–Doppler and chirp scaling algorithms. Each algorithm presents its own advantages and disadvantages considering efficiency and image quality; thus, we aim to introduce some of the most common SAR image formation algorithms and compare them based on these two aspects. Depending on the requisites of each individual system and implementation, there are many device options to choose from, for instance, FPGAs, GPUs, CPUs, many-core CPUs, and microcontrollers. We present a review of the state of the art of SAR imaging systems implementations. We also compare such implementations in terms of power consumption, execution time, and image quality for the different algorithms used.

Grid multi-scroll attractors possess distinctive properties in complex topologies and functions, yet their generation mechanisms in the neural networks still need further exploration. This paper presents a novel method to generate the grid multi-double-scroll attractors within the neural networks. Firstly, a new magnetized Hopfield neural network (HNN) model under the influence of electromagnetic radiation is developed. This model utilizes an electromagnetic radiation control method based on a multi-piecewise memristor to efficiently regulate the number of single direction multi-double-scroll attractors. Secondly, the above proposed magnetized HNN model combined with a memristive self-connection synapse is constructed by using another multi-piecewise memristor to simulate the autapse of a neuron. This combined HNN model with the double multi-piecewise memristors demonstrates the grid multi-double-scroll attractors and the initial-offset behaviors. Finally, the feasibility of the proposed magnetized HNN model is verified by the FPGA platform.

In the era of pervasive multimedia communication, image data has become a dominant form of information exchange across embedded, mobile, and IoT platforms. This surge in visual data transmission introduces critical challenges related to confidentiality, authenticity, and tamper resistance particularly in resource-constrained environments where conventional cryptographic solutions may prove computationally intensive. To address these challenges, lightweight cryptographic algorithms tailored for image protection are essential, balancing rigorous security requirements with efficient hardware and software implementation. This paper proposes a novel lightweight block cipher optimized for image encryption, employing a multi-stage internal Addition-Rotation-XOR (ARX) structure within each round to enhance confusion and diffusion. The cipher operates on 64-bit plaintext blocks with a 64-bit master key and utilizes a customized key schedule mechanism that generates five distinct subkeys per round through bit-swapping, modular addition, and XOR operations. The cryptographic properties of the proposed cipher were evaluated using the NIST SP 800-22 statistical test suite, confirming high key randomness. Further analysis demonstrated robust security with a 50% average avalanche effect, a maximum differential probability of approximately , and a maximum linear bias below . The cipher achieves strong resistance to differential and linear cryptanalysis within five rounds, offering an optimal balance between security and efficiency. Comprehensive statistical analysis using various input images are analyzed and demonstrate the cipher’s robustness in securing visual data. The encryption algorithm was further implemented on an Artix-7 FPGA, and synthesis results confirmed its suitability for resource constrained environments. The results indicate that the proposed cipher offers a secure and efficient solution to modern image security challenges.

This paper presents a novel design of a 21-level switched diode multilevel inverter using a High-Frequency Link (HFL) and a single DC source. The inverter structure consists of 10 power switches and 2 diodes, which significantly reduces the number of components compared to existing topologies. Despite the utilization of HFL for generating multiple voltages, the analysis reveals that the majority (65%) of the power is directly drawn from the single DC source, while only a small portion (35%) passes through the HFL. This reduces the size of the high-frequency transformer and the need for a large DC-DC converter. The proposed topology achieves 21 levels with a low output total harmonic distortion (THD) of 3.99% without the use of additional filters. These features make it suitable for various applications, including electric vehicles and motor systems. Graphical Abstract

Sensors provide data which need to be processed after acquisition to remove noise and extract relevant information. When the sensor is a network node and acquired data are to be transmitted to other nodes (e.g., through Ethernet), the amount of generated data from multiple nodes can overload the communication channel. The reduction of generated data implies the possibility of lower hardware requirements and less power consumption for the hardware devices. This work proposes a filtering algorithm (LDSI—Less Data Same Information) which reduces the generated data from event-based sensors without loss of relevant information. It is a bioinspired filter, i.e., event data are processed using a structure resembling biological neuronal information processing. The filter is fully configurable, from a “transparent mode” to a very restrictive mode. Based on an analysis of configuration parameters, three main configurations are given: weak, medium and restrictive. Using data from a DVS event camera, results for a similarity detection algorithm show that event data can be reduced up to 30% while maintaining the same similarity index when compared to unfiltered data. Data reduction can reach 85% with a penalty of 15% in similarity index compared to the original data. An object tracking algorithm was also used to compare results of the proposed filter with other existing filter. The LDSI filter provides less error (4.86 ± 1.87) when compared to the background activity filter (5.01 ± 1.93). The algorithm was tested under a PC using pre-recorded datasets, and its FPGA implementation was also carried out. A Xilinx Virtex6 FPGA received data from a 128 × 128 DVS camera, applied the LDSI algorithm, created a AER dataflow and sent the data to the PC for data analysis and visualization. The FPGA could run at 177 MHz clock speed with a low resource usage (671 LUT and 40 Block RAM for the whole system), showing real time operation capabilities and very low resource usage. The results show that, using an adequate filter parameter tuning, the relevant information from the scene is kept while fewer events are generated (i.e., fewer generated data).