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This paper presents measurement of third order intermodulation distortion and third order intercept (TOI) in a Fabry–Perot semiconductor laser lasing at 1550.3 nm when the laser is biharmonically bias-current modulated. Keeping the modulation current of one signal fixed, the third order intermodulation power at two different frequencies has been found to increase with the increase in second signal modulation power. There is an eventual crossover or tendency to crossover in the intermodulation characteristics when the modulation current amplitudes of the channels assume the same value. The TOI has been experimentally measured. The intermodulation power appearing at two different frequencies along with their signal power dependence and measurement of TOI constitute the outcome of this paper. The typical value of spurious-free dynamic range of the modulation scheme is 70 dB.

Recent trend researches provide potential results of tunnel field effect transistors (TFETs) for being used in many electronic circuit applications. This work studies the comparative analyses of n+ pocket vertical TFET and dual MOSCAP (D-MOS) vertical TFET to determine their compatibility in RF applications. Synopsys TCAD simulation result shows a better I ON / I OFF ratio (8.43 × 10 8 ), steeper sub-threshold swing (18.67 mV/dec) and an enhanced ambipolarity behavior of the proposed D-MOS VTFET. A comprehensive investigation of both the devices under consideration is performed and comparison has been made on their linearity and intermodulation distortion performances. Certain figure of merits of RF performance such as their higher order transconductance characteristics, second- and third-order voltage intercept points (VIP 2 and VIP 3 ), third-order input intercept point (IIP 3 ), third-order intermodulation distortion (IMD 3 ), 1 dB compression point and total harmonic distortions have been explored in this work. From the analyses performed, the proposed dual MOSCAP VTFET is found to be comparatively linear where minimum intermodulation distortions and lesser higher order harmonics are guaranteed. Finally, the status of the proposed TFET is highlighted as an efficient device for RF circuit applications.

This paper demonstrates the analytical approach of Linearized Radio over Fiber (RoF) link based on Dual-Drive Dual Parallel Mach Zehnder Modulator (DD-DPMZM) by properly adjusting the phase shifters and biasing of the Mach Zehnder Modulator (MZM). Two input RF Source at 7 and 8 GHz applied in the used RoF link. The proposed RoF link consists of Mach Zehnder Modulator (MZM), Parallel combination of Mach Zehnder Modulators, optical fiber, and photodetector (PD). Third Order Intermodulation Distortions (IMD3) factor act as a major issue, which is responsible as performance degradation factor. Major sources of IMD3 spurious components have been investigated and suppressed in theoretical analysis before photodetection. The proposed method is designed with the help of OptSim simulation software, to confirm and validate the analytical analysis and simulation results. Analytical analysis & simulation results show that, 40 dB suppression found in IMD3 spurious components, and 30 dB.Hz 2/3 enhancement found in Spurious Free Dynamic Range (SFDR), for the proposed linearized RoF link as compared to conventional MZM RoF link. The Measured SFDR is also founded as 26 dB.Hz 2/3 , 5 dB.Hz 2/3 , & 10 dB.Hz 2/3 for different optical fiber impairments as 8 km, 10 km & 15 km respectively for used DD-DPMZM based RoF link.

The negative capacitance effect on MOS transistors has lately gained lot of momentum due to the use of ferroelectric material in the gate. They have attracted much attention from researchers due to their improved performance at low power supplies. This work presents the simulation and analysis of NC-CyJLT for analog/RF, linearity distortion, and thermal stability. The analytical modeling of surface potential using the parabolic approximation and Landau-Khalatnikov (L-K) equation has been performed and compared with simulation results. This device combines the advantages of negative capacitance, surrounding gate, and junction-less techniques together, resulting in improved performance and reliability. Analog/RF and linearity distortion analysis of NC-CyJLT have been compared with conventional CyJLT to study the effect of negative capacitance. Further, thermal analysis of NC-CyJLT has been performed to study its operation over a wide range of temperatures. Through analysis, it has been observed that the use of ferroelectric material in the gate stack improves electrostatic, analog/RF performance in comparison to the conventional CyJLT. The simulation results also reveal that the NC-CyJLT device has reduced transconductance derivatives (g m2 and g m3 ), intermodulation distortion 3 (IMD 3 ), and increased voltages intercept points (VIP 2 and VIP 3 ). The input intercept point 3(IIP 3 ) also increases, thus indicating improved linearity performance with reduced distortion. Thermal stability analysis suggests that NC-CyJLT's performance degrades with an increase in temperature beyond the Curie temperature of the ferroelectric material. Hence, the analysis and study of the NC-CyJLT device confirms that the device finds application in low power and high-density analog/RF circuits.

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Graphene field-effect transistors (GFETs) based on ballistic transport represent an emerging nanoelectronics device technology with promise to add a new dimension to electronics and replace conventional, silicon technology, especially for radiofrequency applications. The radiofrequency (GHz) static linearity and nonlinearity performance potential of GFETs is analyzed herein in the ballistic transport regime by exploring their static linearity mathematically in the quasiballistic transport regime along with their scaling potential at four different channel lengths. The proposed model explores linked mathematical expressions for the harmonic distortion, intermodulation distortion, and intercept points, which are depicted in graphical form. The second- and third-order harmonics and intermodulation distortions are analyzed with the help of a mathematical analysis of the drain current equation formulated using McKelvey’s flux theory. The presented expressions are validated based on the nonlinear output characteristic curves of the drain current versus the drain voltage for channel lengths of 140, 240, 300, and 1000 nm. The nonlinearity effect and its impact on the use of quasiballistic and ballistic GFETs for radiofrequency electronic applications is one of the important prospects and is tabulated in Table 1 for greater clarity using the particular models and their respective frequencies. Table 1 The nonlinearity characteristics of GFETs for high-frequency operation Ref. Operating frequency IIP3 (dBm) Conversion loss (dB) L (μm) [ 32 ] 10 MHz 13.8 ~ 30–40 2 [ 33 ] 30 GHz 12.8 19 0.5 [ 34 ] NA 4.9 20–22 1 [ 35 ] NA 22 ~ 15 0.25 [ 35 ] NA 27 10 2 [ 36 ] 2 GHz 19 5 0.75 [ 37 ] 4.3 GHz 30 10 0.24 [ 38 ] 300 MHz 20 15 0.5 [ 39 ] NA 17 17 2.4 [ 24 ] NA 13.8 22 0.44 Proposed 30 GHz 12.6 18.4 0.14 Proposed 30 GHz 12.8 18.8 0.30

To explore single-electron circuits for different applications, a proper simulation platform where circuits consisting of single electron transistors and other devices can be simulated efficiently is needed. A macro model of single electron transistor featuring symmetric tunnel junctions is proposed. In the proposed model, a voltage controlled current source is incorporated in the existing model of SET to get more accurate results. Three scaling factors have been included in the model to improve the versatility of the model. The advantages and disadvantages of different simulation methods are discussed as a justification for choosing the macro model approach. The proposed model can efficiently describe the physical phenomena occurring in coulomb blockade and coulomb oscillation regions. The SPICE environment is used for the simulation and to verify the accuracy, the model is applied to a single electron inverter circuit and the effect of macro model parameters on the noise margin is investigated to estimate the robustness of the inverter cell. A multi peak negative differential resistance circuit based on the proposed macro model is designed and demonstrated. Also, an integrator circuit has been designed to prove the validity of the proposed model in the analog domain. Further, the linearity of the integrator circuit is analyzed through harmonic and intermodulation distortion analysis.

Passive intermodulation (PIM) has become a threat to high‐power and multiple‐channel communication systems as self‐interference sources. A communication channel model with high‐order PIM interference is proposed in this letter. Considering the nonignorable additive white Gaussian noise in communication systems, an extended model for PIM interference based on modified Cauchy and Gaussian mixture distributions is presented. A closed form for bit error rate (BER) is derived based on the statistical model of PIM. The BER performance of the proposed distribution model outperforms the existing analysis methods and approximates the simulated results. This research is of practical significance for communication system design and link margin analysis. A closed form for bit error rate (BER) is derived based on the statistical model of PIM. The comparisons between analytical BER and simulated BER under different conditions ‐ different orders of PIM and different INRs are respectively given to verify the rationalization of the proposed PDF model. This research is of practical significance for communication system design and link margin analysis.

An integrated downconversion CMOS mixer incorporating a comprehensive compensation scheme is presented which aims to minimise second-order intermodulation distortion (IMD2). Unlike previously reported IMD2 calibration schemes which tune only one nonlinear factor at a time, the presented solution allows simultaneous adjustment of several different factors thus achieving a better compensation. The mixer has been implemented in UMC 0.18 µm CMOS to verify the proposed scheme and for comparison with alternative compensation methods. Measurements show that the solution described can improve the input intercept point (IIP2) by over 20 dB while maintaining good amplification and noise performance. IMD2 calibration results are presented and show useful advantages over other approaches. To the best of the authors' knowledge, this scheme for IMD2 calibration has not been previously reported.