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Finite Control Set Model Predictive Control emerges as a promising method for controlling power electronics inverters, outperforming traditional linear techniques. However, implementing Finite Control Set Model Predictive Control on conventional processors faces a significant computational burden due to its repetitive nature. This paper presents a novel approach that utilizes LabVIEW & Field Programmable Gate Arrays to address this computational bottleneck. By capitalizing on the inherent parallelism and suitability of Field Programmable Gate Arrays for discrete control problems, substantial computational advantages are achieved for Finite Control Set Model Predictive Control. The use of LabVIEW, a well-established platform in industrial and commercial solutions, ensures that this work is relevant not only academically but also for real-world industrial applications of FCS-MPC in power electronics and motor drives. This research successfully demonstrates the application of Finite Control Set Model Predictive Control for controlling the current of a motor-like load for a three-phase Voltage Source Inverter system in LabVIEW. To simplify the traditionally complex Field Programmable Gate Arrays programming process, user-friendly toolkits such as LabVIEW Control Design & Simulation, LabVIEW Real-Time, and LabVIEW FPGA Module are employed. This LabVIEW-based integration facilitates the execution of both concurrent and sequential Field Programmable Gate Arrays algorithms, leading to efficient Field Programmable Gate Arrays resource management and user-defined restrictions on maximum switching frequency, obviating the need for resource-intensive control methods for fast switches such as SiC and GaN IGBTs. The proposed controller is validated using an off-the-shelf computer turned into a real-time system but also on Field Programmable Gate Arrays for comparison purposes.

This paper presents the development and experimental validation of a custom Field-Programmable Gate Array (FPGA)-based hardware-in-the-loop (HIL) emulator for high-power induction motor drives. The proposed system enables real-time emulation of a variable-frequency drive consisting of a diode rectifier, a two-level voltage source inverter (VSI), and a 215 HP induction machine. The emulator is implemented on an NI PCIe-7857R FPGA platform using LabVIEW FPGA and fixed-point arithmetic optimised for Kintex-7 resources. A key contribution of this work is the achievement of a 100 ns real-time simulation time step for the converter and machine models, enabling accurate representation of fast switching dynamics while avoiding aliasing effects typically encountered in HIL systems. A multi-rate architecture is adopted to allocate appropriate sampling frequencies to different subsystems, improving computational efficiency and stability. Experimental results obtained from a closed-loop setup with an sbRIO-based controller demonstrate accurate emulation of inverter operation, induction machine dynamics, and controller interactions. The developed platform also enables detailed investigation of switching phenomena, such as voltage spikes, dead-time effects, and current ripple. Comparative validation with a Typhoon HIL 602+ platform confirms similar dynamic behaviour and harmonic performance, demonstrating that the proposed low-cost FPGA-based solution provides a flexible and high-fidelity alternative for real-time power electronics research and controller development.

With the growth of the internet of things (IoT), many challenges like information security and privacy, interoperability/standard, and regulatory and legal issues are arising. This work focused on the information security issue, which is one of the primary challenges faced by connected systems that needs to be resolved without impairing system behaviour. Information, which is made available on the Internet by the things, varies from insensitive information (e.g., readings from outdoor temperature sensors) to extremely sensitive information (e.g., video stream from a camera) and needs to be secured over the Internet. Things which utilise cameras as a source of information pertain to a subclass of the IoT called IoVT (internet of video things). This paper presents secured and unsecured video latency measurement results over the Internet for a marine ROV (remotely operated vehicle). A LabVIEW field programmable gate arrays (FPGAs)-based bump-in-the-wire (BITW) secure core is used to provide an AES (advanced encryption standard)-enabled security feature on the video stream of an IoVT node (ROV equipped with a live-feed camera). The designed LabVIEW-based software architecture provides an option to enable/disable the AES encryption for the video transmission. The latency effects of embedding encryption on the stream with real-time constraints are measured and presented. It is found that the encryption mechanism used does not greatly influence the video feedback performance of the observed IoVT node, which is critical for real-time secure video communication for ROV remote control and piloting. The video latency measurement results are taken using 128, 256 and 512 bytes block lengths of AES for both H.264 and MJPEG encoding schemes transmitted over both TCP and UDP transmission protocols. The latency measurement is performed in two scenarios (i.e., with matching equipment and different equipment on either end of the transmission).

There has recently been an increase in the number of new chaotic system designs and chaos-based engineering applications. In this study, since homoclinic and heteroclinic orbits did not exist and analyses like Shilnikov method could not be used, a 3D chaotic system without equilibrium points was included and thus different engineering applications especially for encryption studies were realized. The 3D chaotic system without equilibrium points represents a new different phenomenon and an almost unexplored field of research. First of all, chaotic system without equilibrium points was examined as the basis and electronic circuit application of the chaotic system was realized and oscilloscope outputs of phase portraits were obtained. Later, chaotic system without equilibrium points was modelled on Labview Field Programmable Gate Array (FPGA) and then FPGA chip statistics, phase portraits and oscilloscope outputs were derived. With another study, VHDL and RK-4 algorithm were used and a new FPGA-based chaotic oscillators design was achieved. Results of Labview-based design on FPGA- and VHDL-based design were compared. Results of chaotic oscillator units designed here were gained via Xilinx ISE Simulator. Finally, a new chaos-based RNG design was achieved and internationally accepted FIPS-140-1 and NIST-800-22 randomness tests were run. Furthermore, video encryption application and security analyses were carried out with the RNG designed here.

Early detection of breast cancer saves lives. Existing detecting techniques are invasive. Electrical bioimpedance is a noninvasive technique and has a high diagnostic potential. An impedance value different from the normal can predict a physiological abnormality. The idea is to use a designed bioimpedance device to early detect breast cancer. A low-frequency current (1 kHz, 0.9 mA) is injected to each breast to measure the extracellular resistances. The resistances of the two breasts are then measured, and if there is a significant difference, warning is displayed. The performance was tested on a set of reference resistors, and the validation was done in vitro on (Na+Cl-) solutions and in vivo on a group of forty volunteer women. The results confirm that the electrical conductivity of an ionic solution is proportional to its concentration. The concentration and the resistance are strongly correlated (correlation coefficient of 0.97). The accuracy and the repeatability of the measures were satisfactory. Early detection means that we can detect small extracellular concentration variations into the breast (from 0.6 g/l). In vivo measurements made it possible to set the threshold at 50 ohm. If the difference between the two measured breast resistances is greater than this threshold, we advise the patient to consult a doctor promptly. The difference between measured resistances of the right and left breast is a pertinent parameter to early detect the presence of a cancer. The lowest resistance value (RR or RL) can provide information on the breast affected by the cancer (right or left). Various improvements in the system are possible but already the results are encouraging. In the future, this system could be integrated into a bra.

Fiber-optic hydrophones with interferometric interrogators are widely used for highly sensitive underwater acoustic sensing. Many such reported interrogators that are suitable either for a single hydrophone or an array of hydrophones are mostly built with measurement-specific multiplexing schemes. However, in realistic field operations, large-fiber-optic sonar array systems are used. Such systems necessitate high-speed hybrid interrogators that can be used to characterize single hydrophones in addition to the interrogation of the entire hydrophone array. This paper reports such a cost-effective hybrid FPGA-based fiber-optic interrogator with a hybrid TDM–DWDM multiplexing scheme and rapidly deployable LabVIEW® codes for interrogating single or large hydrophone arrays. Subsequently, a 2 × 2 array system is realized and used for performance validation of the developed interrogator. The factors leading to the interrogator noise characteristics are analyzed, and the design methodology is adopted for optimal performance. The performance of the system is examined and has yielded a phase noise of about −90 dB ref.1 rad/√Hz at 1 kHz for a hybrid DWDM–TDM array configuration while better than −105 dB ref. 1 rad/√Hz at 1 kHz for a single hydrophone configuration that results in a net noise equivalent pressure close to deep sea state zero (DSS0) level.

with the increasing market demand and rapid development of aircraft technology, more electric concept has become an important trend for the future development of aircraft. Therefore, motors are widely applied in the aviation field increasingly. This paper mainly introduces the hardware environment and LabVIEW implementation process in the development of aviation high speed and high voltage BLDCM control system based on NI hardware and software platform. The test shows the control system is able to realize effective control over aviation BLDCM. This system is highly flexible and can lay a foundation for the algorithms used in subsequent related research efforts.

Surface electromyography (sEMG) signal processing has been the subject of many studies for many years now. These studies had the main objective of providing pertinent information to medical experts to help them make correct interpretations and medical diagnoses. Beyond its clinical relevance, sEMG plays a critical role in human–machine interface systems by monitoring skeletal muscle activity through analysis of the signal’s amplitude envelope. Achieving accurate envelope detection, however, demands a robust and efficient signal processing pipeline. This paper presents the implementation of an optimized processing framework for the real-time linear envelope detection of sEMG signals. The proposed pipeline comprises three main stages, namely data acquisition, full-wave rectification, and low-pass filtering, where the deterministic execution time of the algorithm on the FPGA (98 ns per sample) is two orders of magnitude faster than the data acquisition sample interval (200 µs), guaranteeing real-time performance. The entire algorithm is designed for deployment on the FPGA core of a CompactRIO embedded controller, with emphasis on achieving high accuracy while minimizing hardware resource consumption. For this purpose, a parallel second-order structure of the Butterworth low-pass (LP) filter is proposed. The designed filter is tested and compared practically to the conventional method, which is the moving average (MAV) filter. The mean square error (MSE) is used as a metric for performance evaluation. From the analysis, it is observed that the proposed design LP filter shows an improved MSE and reduced hardware resources than the MAV filter. Furthermore, the comparative analysis and the results show that our proposed design LP filter is a valid and reliable method for linear envelope detection.

Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.

This article presents a complete test equipment for the promising on-board serial high-speed SpaceFibre protocol, published by the European Committee for Space Standardization. SpaceFibre and SpaceWire are standard communication protocols for the latest technology sensor devices intended for on-board satellites and spacecrafts in general, especially for sensors based on image acquisition, such as scanning radiometers or star-tracking devices. The new design aims to provide the enabling tools to the scientific community and the space industry in order to promote the adoption of open standards in space on-board communications for current- and future-generation spacecraft missions. It is the first instrument expressly designed for LabVIEW users, and it offers tools and advanced features for the test and development of new SpaceFibre devices. In addition, it supports the previous SpaceWire standard and cross-communications. Thanks to novel cutting-edge design methods, the system complex architecture can be implemented on natively supported LabVIEW programmable devices. The presented system is highly customizable in terms of interface support and is provided with a companion LabVIEW application and LabVIEW Application Programming Interface (API) for user custom automated test-chains. It offers real-time capabilities and supports data rates up to 6.25 Gbps.The proposed solutions is then fairly compared with other currently available SpaceFibre test equipment. Its comprehensiveness and modularity make it suitable for either on-board device developments or spacecraft system integrations.