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With the growing importance of subways in public transportation, Tunnel Boring Machine (TBM) has been widely used in subway construction due to its efficiency and reliability. The Advance Rate (AR) is a key performance indicator for TBM, and accurate AR prediction is crucial for optimizing shield tunneling operations. This paper proposes a real-time AR prediction method for double-line subway projects, using data from the Shenzhen–Dayawan Intercity Line at Bainikeng Station. The method employs Wavelet Denoising (WD) for data preprocessing and develops a time series data structure scheme to enhance prediction accuracy. GWO-BiLSTM algorithm combination is first applied to tunneling prediction and benchmarked against seven conventional machine learning and deep learning algorithms. Three evaluation metrics (R 2 , MAE, and RMSE) are used to comprehensively assess the model’s performance. The proposed method achieves an R 2 of 0.98022, with MAE and RMSE values of 2.1139 and 2.9527, respectively, indicating a significant improvement over other models. The improvements in data processing, time series data structuring, and algorithm integration demonstrate the superiority of the proposed method. This flexible and adaptive approach can be tailored to various geological conditions, ensuring broad applicability across different engineering contexts for effective AR prediction.

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

In this paper, we propose a novel structure with Control Source and Control Gate structured tunnel field-effect transistor (CSCG‑iTFET), which achieves an unprecedentedly steep subthreshold swing (SS) while maintaining high ON-state current ( ). In addition, using Schottky contacts at the source without doping reduces leakage current and thermal budget. We compared the performance of four different device structures, including conventional Double Gate TFET with Control Gate, iTFET with Control Gate, iTFET with Charge Enhancement Layer and Control Gate, and our structure. The accumulation layer can be enhanced by using the characteristic of Control Source to modulate the voltage. We performed simulation studies using Sentaurus TCAD. Utilize calibrated models for accurate simulations, exploiting the same referenced processes, demonstrate that the Control Source iTFET exhibits an average subthreshold swing S.S AVG of 9.69 mV/Dec and a minimum subthreshold swing S.S MIN of 1.72 mV/Dec, respectively. At V D = 0.2 V, the I ON current is 2.95 × 10 − 7 A/µm, and the I ON / I OFF ratio is 3.84 × 10 9 . It is believed that the performance can be further improved if the fabrication processes are optimized.

In this work, we investigate the impact of quantum confinement effects (QCE) on the recently proposed Control Source and Control Gate Structured Tunnel Field-Effect Transistor (CSCG-iTFET), extending beyond conventional semiclassical TCAD analysis. By incorporating a self-consistent Schrödinger–Poisson quantum correction into device simulations, we systematically examine how quantum confinement influences the drive current in ultra-thin semiconductor devices. This is the first work that systematically quantifies the influence of QCE on CSCG-iTFET performance. Results reveal that although quantum confinement widens the bandgap and suppresses I ON , the CSCG-iTFET retains an exceptionally steep subthreshold swing (27.3 mV/dec) and negligible I off degradation, outperforming conventional TFET architectures under equivalent scaling. These findings demonstrate that the CSCG-iTFET remains a viable candidate for IRDS-defined ultra-low-power nodes even under severe quantum constraints, and provide physical insight into the limits of scalability for line-tunneling TFETs.

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at VD = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SSavg) of 30.5 mV/dec, an Ion of 3.12 × 10–5 A/μm and an Ion/Ioff ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (Ids) versus gate-source voltage (Vgs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (GTAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate GTAT using the standard Schenk model. The GTAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s Ids–Vgs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental Ids–Vgs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance.

In this paper, an In0.53Ga0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N+-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N+-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (IOFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control IOFF. By optimizing various parameters related to the N+-pocket and the gate electrodes, DGNP-EHBTFET’s IOFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.