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Programmable circuit components are indispensable for nanomagnet logic (NML, also called magnetic quantum-dot cellular automata) devices. Two alternative programmable majority gates (PMGs) (PMG1 and PMG2) for in-plane NML are proposed. The presented designs both utilise trapezoid shape nanomagnets (nanomagnet with a slanted edge) to form the structures. With only a uniform layout and a homogeneous clocking field, the proposed structures can orderly reconfigure eight input combinations of the majority gates, and they also demonstrate superior performance over the regular shape nanomagnet-based PMG. The innovative design could find technological application in the field of majority gate-based programmable magnetic circuits (e.g. programmable nanomagnetic Full Adder).

Quantum-dot Cellular Automata (QCA) is a new nanoscale computing architecture that has ultra-low power, high device density, and possible applicability to future nano-communication systems. In this paper, we present optimized QCA-based even parity generator and parity checker circuits with efficient XOR logic. The proposed designs reduce area and cell count significantly while maintaining stable logical operation. The circuits were drawn and simulated in QCADesigner-E and analyzed using QCAPro for energy dissipation and polarization error. Results show that the proposed parity generator reduces 57% cell count and 20% area over existing designs, whereas the parity checker reduces 67% cell count and 12.5% area. These improvements indicate the potential of the proposed circuits for low-power and small-area error detection mechanisms in nanoscale communication systems.

All optical logic gates are building blocks for all optical data processors. One way of designing optical logic gates is using threshold switching which can be realized by combining an optical resonator with nonlinear Kerr effect. In this paper we showed that a novel structure consisting of nonlinear photonic crystal ring resonator which can be used for realizing optical NAND/NOR and majority gates. The delay time of the proposed NAND/NOR and majority gates are 2.5 ps and 1.5 ps respectively. Finite difference time domain and plane wave expansion methods were used for simulating the proposed optical logic gates. The total footprint of the proposed structure is about 988 μm

Quantum-dot Cellular Automata (QCA), is a contemporary nanotechnology for manufacturing logical circuits which brings less power consumption, smaller circuit size, and faster operation. In this technology, logical gates are composed of nano-scale basic components called cells. Each cell consists of four quantum-dot arranged in a square pattern. Diagonal arrangement of two extra electrons resembles two logical states 0 and 1. Majority gate and inverter gate are considered as the two most fundamental building blocks of QCA. The effect of cells on their neighbor cells enables designing more diverse circuits. Multiplexer is a key component in most computer circuits. Researchers have presented various QCA designs for multiplexers since the introduction of QCA. In this research all presented designs are simulated in QCA Designer Version 2.0.3 and investigated from different aspects such as number of cells, size, types of components used in circuit, number of layers, and number of cycles for producing output.

Semiconductor optical amplifier-based polarization rotation is utilized in designing all-optical AND gate at 100 Gbps. The AND gate shows high extinction ratio (ER ∼ 15 dB), contrast ratio (CR ∼ 18 dB) and quality factor (Q-factor ∼ 16 dB). The effect of the amplified spontaneous emission noise on the performances is also investigated. The AND gate has relative eye opening (REO) varying from 93.52 to 97.1% for 10–30 dB unsaturated gain. Using the AND gate a majority voting gate is designed and analyzed and has Q ∼ 11.7 dB with REO ∼ 91%.

The article introduces a revolutionary Nanorouter structure, which is a crucial component in the Nano communication regime. To complete the connection, many key properties of Nanorouters are investigated and merged. QCA circuits with better speed and reduced power dissipation aid in meeting internet standards. Cryptography based on QCA design methodologies is a novel concept in digital circuit design. Data security in nano-communication is crucial in data transmission and reception; hence, cryptographic approaches are necessary. The data entering the input line is encrypted by an encoder, and then sent to the designated output line, where it is decoded and transferred. The Nanorouter is offered as a data path selector, and the proposed study analyses the cell count of QCA and the circuit delay. In this manuscript, novel designs of (4:1)) Mux and (1:4) Demux designs are utilized to implement the proposed nanorouter design. The proposed (4:1) Mux design requires 3–5% fewer cell counts and 20–25% fewer area, and the propsoed (1:4) Demux designs require 75–80% fewer cell counts and 90–95% fewer area compared to their latest counterparts. The QCAPro utility is used to analyse the power consumption of several components that make up the router. QCADesigner 2.0.3 is used to validate the simulation results and output validity.

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of 0.02 μ m 2 and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.

Since conventional CMOS technology has met its development bottleneck, an alternative technology, quantum-dot cellular automata (QCA), attracted researchers’ attention and was studied extensively. The manufacturing process of QCA, however, is immature for commercial production because of the high defect rate. Seeking for designs that display excellent performance shows significant potentials for practical realizations. In the paper we propose a 5 × 5 module, which not only can implement three-input majority gate but also can realize five-input majority gate by adding another two inputs. A comprehensive analysis is made in terms of area, number of cells, energy dissipation and fault tolerance against single-cell omission defects. In order to testify the superiority of the proposed designs, preexisting related designs are tested and compared. Weighing up above four kinds of factors and technical feasibility, proposed majority gates perform fairly well. Further, we take full adders and multi-bit adders as illustrations to display the practical application of proposed majority gates. The detailed comparisons with previous adders reveal that proposed 5 × 5 module behaves well in circuits, especially the high degree of fault tolerance and the relatively small area, complexity and QCA cost, thereby making it more suitable for practical realizations in large circuit designs.

Quantum-dot cellular automata (QCA) which is a suitable alternative to conventional CMOS technology is susceptible to some defects in chemical synthesis and deposition phases of circuit fabrication. Besides, the majority gate is one of the most important primary gates for designing digital circuits in this emerging technology. Designing a fault-tolerant majority gate is one of the hot topics in QCA technology. Most previous works tried to improve the majority gate reliability by increasing the number of QCA cells which resulted in occupying more area. In this paper we propose a novel area-efficient three-input majority gate which can tolerate the single-cell omission and extra-cell deposition defects by 86% and 75%, respectively. The proposed majority gate consists of 11 simple QCA cells with 0.006 µ m 2 and 1.62 e-002 MeV area and energy consumption, respectively. A complete fault tolerance analysis for our proposed majority gate against cell omission, extra-cell deposition, and cell displacement and misalignment defects is also provided. We design a fault-tolerant coplanar fulladder/fullsubtractor and a two-to-one multiplexer using the proposed majority gate and compare it with the same previous works. Simulation results from QCADesigner 2.0.3 and QCADesigner-E show that in all cases our proposed robust circuits can reduce the area consumption. Finally, we implement a fault-tolerant coplanar one-bit ALU using the proposed circuits that can perform four logical and mathematical operations.

This paper explores the design and simulation of a majority gate with three inputs based on the resonance ring of 2D photonic crystals. The design of this gate uses a ring resonator and four waveguides in a square lattice. This structure is simple and small with dielectric rods of silicon on an air substrate. Low and high logics are defined based on the optical sources being on or off. The large interval between 0 and 1 at the output demonstrates the high accuracy of this optical gate. The operating wavelength of the gate is 1.55 µm, which is in the photonic band gap calculated for the gate structure. Calculations are carried out in transverse magnetic (TM) mode using the finite-difference time-domain (FDTD) numerical method.