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Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router design-called SturdiSwitch-to increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.

The metrics suite for object-oriented design put forward by Chidamber and Kemerer (1994) is partly evaluated by applying principles of measurement theory. Using the object coupling measure (CBO) as an example, it is shown that failing to establish a sound empirical relation system can lead to deficiencies of software metrics. Similarly, for the object-oriented cohesion measure (LCOM) it is pointed out that the issue of empirically testing the representation condition must not be ignored, even if other validation principles are carefully obeyed. As a by-product, an alternative formulation for LCOM is proposed.

This chapter contains sections titled: SoC Design Paradigms System Architecture Low-power SoC Design Network-on-Chip based SoC References

Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.This textbook.

Long description: This thesis addresses optimal control of discrete-time switched linear systems with application to networked embedded control systems (NECSs). Part I focuses on optimal control and scheduling of discrete-time switched linear systems. The objective is to simultaneously design a control law and a switching (scheduling) law such that a cost function is minimized. This optimization problem exhibits exponential complexity. Taming the complexity is a major challenge. Two novel methods are presented to approach this optimization problem: Receding-horizon control and scheduling relies on the receding horizon principle. The optimization problem is solved based on relaxed dynamic programming, allowing to reduce complexity by relaxing optimality within predefined bounds. The solution can be expressed as a piecewise linear (PWL) state feedback control law. Stability is addressed via an a priori stability condition based on a terminal weighting matrix and several a posteriori stability criteria based on constructing piecewise quadratic Lyapunov functions and on utilizing the cost function as a candidate Lyapunov function. Moreover, a region-reachability criterion is derived. Periodic control and scheduling relies on periodic control theory. Both offline and online scheduling are studied. The optimization problem is solved based on periodic control and exhaustive search. The online scheduling solution can again be expressed as a PWL state feedback control law. Stability is guaranteed inherently. Several methods are proposed to reduce the online complexity based on relaxation and heuristics. Part II focuses on optimal control and scheduling of NECSs. The NECS is modeled as a block-diagonal discrete-time switched linear system. Various control and scheduling codesign strategies are derived based on the methods from Part I regarding the structural properties of NECSs. The methods presented in Part I and II are finally evaluated in a case study.

With the rapid developments in VLSI technology, the communication channels in networks-on-chip (NoCs) can place many wires for sustaining high-performance requirements over the communication bottleneck in multicore, multiprocessor systems-on-chip (MPSoCs). Consequently, NoC channels, due to increased wire density, are exposed to different logic level faults, e.g., short resulting in reliability and yield issues in NoC-based systems. These faults can appear at any stage of the lifetime of a chip. While existing in an NoC communication architecture, the channel-short faults bring the system into various failures that surprisingly cause a significant deviation from its expected performance. In this work, an online, distributed test solution is presented that detects and diagnoses intra-channel and inter-channel short faults and analyzes the effect of these faults on various performance metrics. Fault simulations ensure up to 100% coverage metrics. Network simulation shows insight into the impact of channel shorts in NoC performances. It is observed that the amount of test time is reduced to 10 × concerning a set of prior works while employed for a group of NoCs. It is also seen on these NoCs that average packet latency is improved by 15.14–46.79% while energy consumption is reduced by 13.68–39.13% by the current solution than the set of existing solutions. Moreover, the proposed solution scales to all NoCs irrespective of size, topology, and channel width at an acceptable test cost.

The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions. * Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends* An integrated presentation not currently available in any other book* A thorough introduction to current design methodologies and chips designed with NoCs

Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.