Journal Article

On the Effects of Process Variation in Network-on-Chip Architectures

Narayanan, V, Dongkook Park, Nicopoulos, C, Irwin, M J, Yanamandra, A, Srinivasan, S, Das, C R

2010

Overview

The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router design-called SturdiSwitch-to increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.

• Publisher: IEEE,IEEE Computer Society
• Subject: Architecture / Arrays / Budgets / Casting / Chip scale packaging / Communication / Computer architecture / Computer engineering / Computer science / Delay / Density / Design / Designers / Digital Object Identifier / Fabrics / Fault tolerance / hardware reliability / Interconnect / interconnection networks / Manufacturing / Multicore processing / Network-on-a-chip / Network-on-Chip (NoC) / Power system interconnection / Process Variation (PV) / Routers / Scalability / Semiconductor devices / Studies / System-on-a-chip / Transistors