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With the advent of portable devices, the demand for static random-access memory (SRAM) is increasing with large use of SRAM in System on Chip and high-performance VLSI circuits. SRAM optimization has become a focal point for research work, as 60% to 70% area of the chip is consumed by the memories. The performance parameters optimization can lead to the overall optimization of the performance of the chip. In this paper design and analysis of the 6T SRAM cell at different technologies using PTM (Predictive Technology Model) model has done with the aim of reducing power dissipation while maintaining stability. Then the performance of SRAM cell is compared on the basis of power dissipation i.e. dynamic power dissipation and static power dissipation, delay, Power Delay Product (PDP) and Static Noise Margin (SNM).SRAM cell read stability and write-stability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. Cell stability is also examined by the calculation of SNM with the help of the butterfly curve method at different CMOS technologies. Effect of variation of channel length on static power consumption, dynamic power consumption, delay, PDP and SNM is also measured. SNM variation is also observed with the variation of the supply voltage.

The plastic deformation behavior of selective laser melting (SLM) 3D printed SS316L steel has been analyzed at the temperature range 25- 1000℃ (25 (room temperature), 200, 400, 600, 800 and 1000℃) and strain rate range 10 −3 -10 3 s −1 (10 −3 , 10 −2 , 10 −1 , 10 0 , 10 1 , 10 2 and 10 3 s −1 ) under compressive loading environments. The flow stress vs. plastic strain results revealed that the flow stress was reduced 136.64% from room temperature to 1000℃ at 10 −3 s −1 . Further, the flow stress was decreased 102.86% from room temperature to 1000℃ at 10 3 s −1 . The flow stress was increased 46.63% from 10 −3 s −1 to 10 3 s −1 at room temperature. Moreover, the flow stress was increased 95.07% from 10 −3 s −1 to 10 3 s −1 at 1000℃. The temperature and strain rate effect on strain rate sensitivity (m) has been observed for SLM 3D printed SS316L steel. Based on strain rate sensitivity (m), the power dissipation efficiency ( ) and instability dimensionless parameter ( ) map plot contours have been investigated under various hot working parameters for SLM 3D printed SS316L steel. Further, hot working processing maps have been generated by superimposing instability dimensionless parameters ( ) map on the power dissipation efficiency ( ) map for SLM 3D printed SS316L steel. The processing map was further related with investigated material microstructure to identify the hot processing safe and unsafe zone for SLM 3D printed SS316L. The unsafe instability region occurred at the low strain rate range (10 −2 – 10 −1 s −1 ), high strain rate range (10 2 -10 3  s −1 ) and temperature range (200–400℃, and 800 − 100℃) for 0.02, 0.04, 0.06, 0.08 and 0.10 strain. Further, the remaining area was useful for hot workability. The Vicker’s hardness revealed that the hardness was decreased with 3.87%, 12.55%, 22.01%, 32.35%, and 43.70% at 200 0 C, 400 0 C, 600 0 C, 800 0 C and 1000 0 C respectively with respect to room temperature hardness.

The use of piezoelectric ceramic transducers (such as Lead-Zirconate-Titanate—PZT) has become more and more widespread for Structural Health Monitoring (SHM) applications. Among all the techniques that are based on this smart sensing solution, guided waves and electro-mechanical impedance techniques have found wider acceptance, and so more studies and experimental works can be found containing these applications. However, even though these two techniques can be considered as complementary to each other, little work can be found focused on the combination of them in order to define a new and integrated damage detection procedure. In this work, this combination of techniques has been studied by proposing a new integrated damage indicator based on Electro-Mechanical Power Dissipation (EMPD). The applicability of this proposed technique has been tested through different experimental tests, with both lab-scale and real-scale structures.

SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.

Increasing the number of transmit antennas can improve the diversity gain of the system, and accordingly reduce the transmit power dissipation. However, the high circuit power dissipation incurred cannot be ignored. Generalised selection combining, which could provide a certain spatial diversity in the transmit diversity systems, performs a good balance between system performance and practical implementation cost. In this study, the authors propose an energy efficient generalised selection combining (EE-GSC) scheme which obtains improved transmitter energy efficiency (EE) by providing a best tradeoff between the diversity gain and the circuit power dissipation of multiple antennas. Based on the classical results of order statistics, a theoretical analysis of EE-GSC performance is carried out in detail over Rayleigh fading channels. Based on this analysis, the average number of active branches as well as the average power dissipation of the proposed scheme is also derived. Numerical results are also given to further illustrate the EE performance of the proposed scheme.

Recent Approximate computing is a change in perspective in energy-effective frameworks plan and activity, in light of the possibility that we are upsetting PC frameworks effectiveness by requesting a lot of precision from them. Curiously, enormous number of utilization areas, like DSP, insights, and AI. Surmised figuring is appropriate for proficient information handling and mistake strong applications, for example, sign and picture preparing, PC vision, AI, information mining and so forth Inexact registering circuits are considered as a promising answer for lessen the force utilization in inserted information preparing. This paper proposes a FPGA execution for a rough multiplier dependent on specific partial part-based truncation multiplier circuits. The presentation of the proposed multiplier is assessed by contrasting the force utilization, the precision of calculation, and the time delay with those of a rough multiplier dependent on definite calculation introduced. The estimated configuration acquired energy effective mode with satisfactory precision. When contrasted with ordinary direct truncation proposed model fundamentally impacts the presentation. Thusly, this novel energy proficient adjusting based inexact multiplier design outflanked another cutthroat model.

In order to improve the light-load efficiency of active clamp forward converter with synchronous rectifier (SR), power loss analysis of the converter operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) are presented in this study. The light-load efficiency of normal ACF converter with SR is low because the output inductor current can go negative when operating in CCM. Considering the fixed frequency control only, to shift the converter's operating mode from CCM to DCM at a critical point of output current at light-load is a solution for efficiency improvement. Based on the CCM and DCM power dissipation models proposed in this study, the power loss characteristics of the converter are analysed, and the critical shift point of output current can be derived, which has also been verified by an experimental prototype.

A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don’t care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS’89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don’t care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.