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A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding
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A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding
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Journal Article
A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding
2016
Overview
A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.
Publisher
Springer US,Springer Nature B.V
Subject
