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If memory hierarchy is stopping your microprocessor from performing at the highest level it should be, then this book will show how to resolve that problem. This book provides the reader with everything they need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy. As a result you will be able to design and emulate the entire memory hierarchy. As a reference, this book is targeted toward both academics and practicing engineers in microarchitecture and computer system design, embedded system design, and low power design.

Presented for the first time is the implementation of independent microfluidic cooling of different tiers in a 3D stack based on their power dissipation. The impact of this approach on heterogeneous 3D IC stacks, such as memory-on-processor and processor-on-processor with different power dissipations, has been experimentally explored. The junction temperature difference between tiers with different power dissipation is decreased from 12 to 7°C. Significant junction temperature reduction and thermal decoupling are achieved by this approach compared to air-cooling.

This book includes a survey of all RFID fundamentals and practices in the first part of the book while the second part focuses on UHF passive technology. This coverage of UHF technology and its components including tags, readers, and antennas is essential to commercial implementation in supply chain logistics and security. Readers of this book should have an electrical engineering background, but have not yet dealt with RFID. To this end, the author is very careful to illustrate all concepts and detail his explanations meticulously. In this way, he will bring the reader along organically showing him/her what to expect, develop, and use while implementing an RFID system.

This book includes papers presented at the International Conference on Materials, Computer Engineering and Education Technology (MCEET 2020, December 19-20, 2020, China). MCEET 2020 provided an excellent international forum for sharing knowledge and results in materials science, machinery design, robotics and mechatronics, computer engineering, information technologies, and education.

A computer built entirely using transistors based on carbon nanotubes, which is capable of multitasking and emulating instructions from the MIPS instruction set, is enabled by methods that overcome inherent challenges with this new technology. Computing with carbon nanotube transistors Carbon nanotubes have long been touted as promising building blocks for computers based on carbon rather than silicon. A main motivation towards this goal is the potential for circuits using carbon nanotube transistors to achieve high energy efficiency. Various carbon nanotube electronic circuit blocks have been demonstrated previously, but Max Shulaker et al . now reach a true milestone in the fields of carbon electronics and nanoelectronics by building a simple but functional computer made entirely from carbon nanotube transistors. Composed of 178 transistors, each containing between 10 and 200 carbon nanotubes, it runs a simple operating system and is capable of multitasking: it performs four tasks (summarized as instruction fetch, data fetch, arithmetic operation and write-back) and can run two different programs concurrently. The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies 1 , 2 . Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems 3 , 4 .

Recent developments in the controlled movement of domain walls in magnetic nanowires by short pulses of spin-polarized current give promise of a nonvolatile memory device with the high performance and reliability of conventional solid-state memory but at the low cost of conventional magnetic disk drive storage. The racetrack memory described in this review comprises an array of magnetic nanowires arranged horizontally or vertically on a silicon chip. Individual spintronic reading and writing nanodevices are used to modify or read a train of ~10 to 100 domain walls, which store a series of data bits in each nanowire. This racetrack memory is an example of the move toward innately three-dimensional microelectronic devices.

Taking aim at silicon Silicon transistors in microelectronics are shrinking to close to the size at which quantum effects begin to have an impact on device performance. As silicon looks certain to remain the semiconductor material of choice for a while yet, such effects may be turned into an advantage by designing silicon devices that can process quantum information. One approach is to make use of electron spins generated by phosphorus dopant atoms buried in silicon, as they are known to represent well-isolated quantum bits (qubits) with long coherence times. It has not been possible to control single electrons in silicon with the precision for qubits, but now Andrea Morello and colleagues report single-shot, time-resolved readout of electron spins in silicon. This is achieved by placing the phosphorus donor atoms near a charge-sensing device called a single-electron transistor, which is fully compatible with current microelectronic technology. The demonstrated high-fidelity single-shot spin readout opens a path to the development of a new generation of quantum computing and spintronic devices in silicon. Electron spins generated by phosphorus dopant atoms buried in silicon represent well-isolated quantum bits with long coherence times, but so far the control of such single electrons has been insufficient to use them in this way. These authors report single-shot, time-resolved readout of electron spins in silicon, achieved by coupling the donor atoms to a charge-sensing device called a single-electron transistor. This opens a path to the development of a new generation of quantum computing and spintronic devices in silicon. The size of silicon transistors used in microelectronic devices is shrinking to the level at which quantum effects become important 1 . Although this presents a significant challenge for the further scaling of microprocessors, it provides the potential for radical innovations in the form of spin-based quantum computers 2 , 3 , 4 and spintronic devices 5 . An electron spin in silicon can represent a well-isolated quantum bit with long coherence times 6 because of the weak spin–orbit coupling 7 and the possibility of eliminating nuclear spins from the bulk crystal 8 . However, the control of single electrons in silicon has proved challenging, and so far the observation and manipulation of a single spin has been impossible. Here we report the demonstration of single-shot, time-resolved readout of an electron spin in silicon. This has been performed in a device consisting of implanted phosphorus donors 9 coupled to a metal-oxide-semiconductor single-electron transistor 10 , 11 —compatible with current microelectronic technology. We observed a spin lifetime of ∼6 seconds at a magnetic field of 1.5 tesla, and achieved a spin readout fidelity better than 90 per cent. High-fidelity single-shot spin readout in silicon opens the way to the development of a new generation of quantum computing and spintronic devices, built using the most important material in the semiconductor industry.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI testing and design-for-testability (DFT) techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly system-on-chip test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Using organic transistors with a floating gate embedded in hybrid dielectrics that comprise a 2-nanometer-thick molecular self-assembled monolayer and a 4-nanometer-thick plasma-grown metal oxide, we have realized nonvolatile memory arrays on flexible plastic substrates. The small thickness of the dielectrics allows very small program and erase voltages ([less-than or equal to]6 volts) to produce a large, nonvolatile, reversible threshold-voltage shift. The transistors endure more than 1000 program and erase cycles, which is within two orders of magnitude of silicon-based floating-gate transistors widely employed in flash memory. By integrating a flexible array of organic floating-gate transistors with a pressure-sensitive rubber sheet, we have realized a sensor matrix that detects the spatial distribution of applied mechanical pressure and stores the analog sensor input as a two-dimensional image over long periods of time.

The von Neumann architecture for a classical computer comprises a central processing unit and a memory holding instructions and data. We demonstrate a quantum central processing unit that exchanges data with a quantum random-access memory integrated on a chip, with instructions stored on a classical computer. We test our quantum machine by executing codes that involve seven quantum elements: Two superconducting qubits coupled through a quantum bus, two quantum memories, and two zeroing registers. Two vital algorithms for quantum computing are demonstrated, the quantum Fourier transform, with 66% process fidelity, and the three-qubit Toffoli-class OR phase gate, with 98% phase fidelity. Our results, in combination especially with longer qubit coherence, illustrate a potentially viable approach to factoring numbers and implementing simple quantum error correction codes.