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"Random access memory"
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Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing
Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge₂Sb₂Te₅). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb₂Te₃) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.
Journal Article
Challenges and Applications of Emerging Nonvolatile Memory Devices
Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.
Journal Article
Demonstration of Synaptic Characteristics in VRRAM with TiN Nanocrystals for Neuromorphic System
To efficiently develop an extremely intensive storage memory, the resistive random‐access memory (RRAM), which operates by producing and rupturing conductive filaments, is essential. However, due to the stochastic nature of filament production, this filamentary type resistive switching has an inherent limitation, which entails the unpredictability of the driving voltage and resistance states. Several strategies such as doping, research into multilayer stacks, and interface engineering, are suggested to tackle this challenge. This work fabricates a CMOS‐compatible TiN/HfOx/TiN‐NCs (nanocrystals)/HfOx/TiN RRAM to implement analog resistive switching and advance the development of the synaptic device. Specifically, atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) are utilized to observe the formation of TiN nanocrystals, which play a crucial role in the enhancement of resistive switching. By comparing HfOx–based RRAM devices with and without NCs, the DC I–V curves, retention, endurance, and switching speed are properly examined. Interestingly, it is found that the TiN/HfOx/TiN‐NCs/HfOx/TiN device is more appropriately utilized as an artificial synapse in neuromorphic systems mainly due to its stable and reliable resistive switching properties. Finally, this work demonstrates well‐controlled resistive switching 3D vertical RRAM with TiN‐NCs, which is particularly suitable for high‐density memory.
Due to the stochastic characteristics of filament formation, HfOx‐based resistive random‐access memory (RRAM) which creates or ruptures filaments to alter the resistance state is regarded as being difficult to stabilize resistive switching. Vertical RRAM with TiN nanocrystals inserted into the switching layer is presented here for it. The linearly variable potentiation and depression features make it appropriate for neuromorphic systems.
Journal Article
Non-Volatile In-Memory Computing by Spintronics
Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since the main bottleneck is from memory, we aim to develop an energy-efficient in-memory computing platform in this book. First, the models of spin-transfer torque magnetic tunnel junction and racetrack memory are presented. Next, we show that the spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect. As a result, by utilizing spintronics, in-memory-based computing has been applied for data encryption and machine learning. The implementations of in-memory AES, Simon cipher, as well as interconnect are explained in details. In addition, in-memory-based machine learning and face recognition are also illustrated in this book.
eBook
Performance-based comparative study of existing and emerging non-volatile memories: a review
The need for high-density, higher-speed memory devices has increased tremendously over the last decade. With scaling and integration capacity of traditional memories reaching its limits, new types of memory technologies have come up in the semiconductor market. These new technologies, i.e. non-volatile memories, aim to solve traditional charge-based memory limitations like low dynamic power, higher BW performance, high density and low scaling cost and also aim to solve low-endurance, process issues. Non-volatile memories play an essential role in transforming the semiconductor industry for future use. This paper aims to describe characteristics of different types of non-volatile memories, ‘available’ and ‘emerging’, in the semiconductor industry. Some recent developments are covered as a part of study in the application of all-optical-enabled MTJ, spin-polarized currents, phase conversion and magnetism in the logic and memory domain. In addition, characteristics of different emerging memories such as all-optical switching MTJ, ReRAM, PCM, SOT-MRAM, STT-MRAM, etc. have been discussed on basis of various performance parameters. Non-volatile memories mentioned above not only provides retention period of over 10 years but also ensures endurance over ~ 10
10
cycles. The read and write operation latency in these memories is between 1 and 7 ns range which is much better as compared to charge-based memories. The literature comparison analysis along with experimental results summary has been presented in this paper.
Journal Article
Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density memory applications
This study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs. By leveraging the floating body effect, this architecture eliminates the need for capacitors, thereby improving integration density and memory performance. Through Sentaurus technology computer-aided design simulations, we compare the PE NS 1T-DRAM device with a conventional NS 1T-DRAM device to evaluate its effectiveness. The results reveal superior retention time (RT) and sensing margin (SM) performance of the proposed PE NS 1T-DRAM device, surpassing the memory criteria outlined by the International Roadmap for Devices and Systems, which requires an RT exceeding 64 ms at 358 K. This enhanced performance of the proposed device is attributed to its extension region, which functions as a potential well for efficient hole storage, as well as the suppression of Shockley‒Read‒Hall recombination. The PE NS 1T-DRAM device also demonstrates robustness to disturbances, maintaining over 89% of its SM and RT under diverse conditions. This superiority is again attributed to its extension region, which minimizes the effects of current flow and electrostatic potential rise. These results highlight the potential of the PE NS 1T-DRAM design for future high-density memory applications.
Journal Article
P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
Die-stacked dynamic random access memory (DRAM) caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main memory. To fully realize their potential, it is essential to improve DRAM cache hit rate and lower its cache hit latency. In order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time, we propose a partial direct-mapped die-stacked DRAM cache called P3DC. This design is motivated by a key observation, i.e., applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency simultaneously. To address this problem, P3DC classifies data blocks into leading blocks and following blocks, and places them at static positions and dynamic positions, respectively, in a unified set-associative structure. We also propose a replacement policy to balance the miss penalty and the temporal locality of different blocks. In addition, P3DC provides a policy to mitigate cache thrashing due to block type variations. Experimental results demonstrate that P3DC can reduce the cache hit latency by 20.5% while achieving a similar cache hit rate compared with typical set-associative caches. P3DC improves the instructions per cycle (IPC) by up to 66% (12% on average) compared with the state-of-the-art direct-mapped cache—BEAR, and by up to 19% (6% on average) compared with the tag-data decoupled set-associative cache—DEC-A8.
Journal Article
1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning
The rapid advancements in the field of autonomous systems have led to a significant demand for artificial‐intelligence‐of‐things (AIoT) edge‐compatible neuromorphic training accelerators with continual/online learning capability. These accelerators require a large network of synaptic elements with high degree of plasticity, high endurance, large integration density, and ultralow programing energy. Although emerging nonvolatile memories exhibit promising potential as synaptic devices, their widespread application in training accelerators is limited due to their low endurance and immature fabrication technology. In contrast, capacitor‐less 1 transistor‐dynamic random‐access memories (1T‐DRAMs) have recently emerged as lucrative alternative to the conventional (1T/1C) DRAMs owing to their high scalability and low footprint. Considering the high endurance, large integration density, and ultralow write energy of the 1T‐DRAMs, in this work, for the first time, their potential is explored as synaptic elements for online learning. The proposed 1T‐DRAM‐based synaptic element exhibits multi‐level capability (up to 6 bits), a large dynamic range (3.91 × 103), an ultralow energy, and an appreciable linearity for potentiation/depression. The 1T‐DRAM‐based synaptic element also exhibits a paired pulse facilitation with an exponential decay similar to the biological synapses. Furthermore, a multilayer perceptron utilizing the proposed 1T‐DRAM synapses achieves an accuracy of 87.10% on MNIST dataset.
This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge‐compatible neuromorphic training accelerators with continual/online learning capability.
Journal Article
Root Security Parameter Generation Mechanism Based on SRAM PUF for Smart Terminals in Power IoT
In the context of the diversity of smart terminals, the unity of the root of trust becomes complicated, which not only affects the efficiency of trust propagation, but also poses a challenge to the security of the whole system. In particular, the solidification of the root of trust in non-volatile memory (NVM) restricts the system’s dynamic updating capability, which is an obvious disadvantage in a rapidly changing security environment. To address this issue, this study proposes a novel approach to generate root security parameters using static random access memory (SRAM) physical unclonable functions (PUFs). SRAM PUFs, as a security primitive, show great potential in lightweight security solutions due to their inherent physical properties, low cost and scalability. However, the stability of SRAM PUFs in harsh environments is a key issue. These environmental conditions include extreme temperatures, high humidity, and strong electromagnetic radiation, all of which can affect the performance of SRAM PUFs. In order to ensure the stability of root safety parameters under these conditions, this study proposes an integrated approach that covers not only the acquisition of entropy sources, but also the implementation of algorithms and configuration management. In addition, this study develops a series of reliability-enhancing algorithms, including adaptive parameter selection, data preprocessing, auxiliary data generation, and error correction, which are essential for improving the performance of SRAM PUFs in harsh environments. Based on these techniques, this study establishes six types of secure parameter generation mechanisms, which not only improve the security of the system, but also enhance its adaptability in variable environments. Through a series of experiments, we verify the effectiveness of the proposed method. Under 10 different environmental conditions, our method is able to achieve full recovery of security data with an error rate of less than 25%, which proves the robustness and reliability of our method. These results not only provide strong evidence for the stability of SRAM PUFs in practical applications, but also provide a new direction for future research in the field of smart terminal security.
Journal Article