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To achieve robust and user friendly software, it is crucial to make sure that Graphical User Interfaces (GUI) is of quality and reliable. The paper suggests a new method of Quasi-Oppositional Genetic Sparrow Search Algorithm (OOGSSA) of generating test cases efficiently in GUI. The ultimate goal is to have multi-objective maximization through various goals of maximum test coverage, reduced redundancy and enhanced fault detection. It is an upgrading of the Sparrow Search Algorithm to combine the imitation of elite opposition based learning with genetic evolution in order to improve the population diversity and convergence rate. The suggested method automatically examines the interactions among GUI events and refines the obtained test suite with the help of adaptive learning. Oogssa is experimental evaluated, with a test suite size of 75, mouse event coverage of 95 and through various test cases with Jaccard Similarity Index (0.75–0.82) and DiceJaroWinkler Dissimilarity (0.18–0.31). OOGSSA has better adaptability which is intelligent as compared to traditional tools of automation testing, dynamic test generation and Non-manual coverage. Notice however its possibility to be costly in terms of computation in the event of very complicated GUI structure. Altogether, OOGSSA offers a scalable and intelligent scheme to test GUI and improve reliability and efficiency in today software.

Research in software testing often involves the development of software prototypes. Like any piece of software, there are challenges in the development, use and verification of such tools. However, some challenges are rather specific to this problem domain. For example, often these tools are developed by PhD students straight out of bachelor/master degrees, possibly lacking any industrial experience in software development. Prototype tools are used to carry out empirical studies, possibly studying different parameters of novel designed algorithms. Software scaffolding is needed to run large sets of experiments efficiently. Furthermore, when using AI-based techniques like evolutionary algorithms, care needs to be taken to deal with their randomness, which further complicates their verification. The aforementioned represent some of the challenges we have identified for this domain. In this paper, we report on our experience in building the open-source EvoMaster tool, which aims at system-level test case generation for enterprise applications. Many of the challenges we faced would be common to any researcher needing to build software testing tool prototypes. Therefore, one goal is that our shared experience here will boost the research community, by providing concrete solutions to many development challenges in the building of such kind of research prototypes. Ultimately, this will lead to increase the impact of scientific research on industrial practice.

C# is one of the most widely used programming languages. However, to the best of our knowledge, there has been no work in the literature aimed at enabling search-based software testing techniques for applications running on the .NET platform, like the ones written in C#. In this paper, we propose a search-based approach and an open source tool to enable white-box testing for C# applications. The approach is integrated with a .NET bytecode instrumentation, in order to collect code coverage at runtime during the search. In addition, by taking advantage of Branch Distance, we define heuristics to better guide the search, e.g., how heuristically close it is to cover a branch in the source code. To empirically evaluate our technique, we integrated our tool into the EvoMaster test generation tool and conducted experiments on three .NET RESTful APIs as case studies. Results show that our technique significantly outperforms gray-box testing tools in terms of code coverage.

Background Multiple factors influence the recovery process of low back pain (LBP). The identification and increased knowledge of prognostic factors might contribute to a better understanding of the course of LBP. The purpose of this study is to investigate the association of the STarT Back Screening Tool (SBST) risk score and the type of leg pain (non-radiating LBP, referred non-radicular, and radicular radiating leg pain) with the disability trajectory (at baseline, the slope, and recovery at one year) in adults with low back pain. Methods This is a prospective cohort study in 347 patients with low back pain who sought physiotherapy care at three primary care practices in the Netherlands. Linear mixed models were estimated to describe the association of the SBST risk score and the type of leg pain with disability at baseline, the slope in the disability trajectory, and at twelve months follow-up. Results A medium/high risk score on the SBST is associated with higher baseline disability scores on the Oswestry Disability Index (ODI), faster initial recovery, and still a higher disability ODI score at 12 months follow-up. Non-radicular referred and radicular radiating leg pain were associated with worse baseline disability ODI scores in LBP. This association was not present for the initial recovery or at the 12 months follow-up. Conclusion The SBST is associated with the LBP recovery trajectory. The SBST might be a useful tool to predict the disability trajectory in a heterogeneous group of people with low back pain in primary care and might, therefore, be recommended in future clinical practice guidelines. The type of leg pain was not associated with the recovery trajectory of LBP. Future research might focus on evaluating different types of leg pain. Trial registration Clinicaltrials.gov: 109,643.

Background Low back pain (LBP) is a top musculoskeletal problem and a substantial cause of socioeconomic burden internationally. The STarT Back Screening Tool (SBST) is a useful screening tool to manage patients with LBP but it is unavailable in Thai. Therefore, the aims of this study were to translate and cross-culturally adapt the SBST into a Thai version (SBST-TH) and validate its psychometric properties (e.g., factor analysis, internal consistency, test-retest reliability, agreement, convergent validity and discriminative validity). Methods Translation and cross-cultural adaptation of the SBST into Thai version were conducted according to standard guidelines. A total of 200 participants with non-specific LBP were invited to complete the SBST, visual analogue scale for pain intensity, Roland-Morris disability questionnaire (RMDQ), fear-avoidance beliefs questionnaire, pain catastrophising scale, hospital anxiety and depression scale and the EuroQol five-dimensional questionnaire. Thirty participants completed the SBST-TH twice with an interval of 48 h to evaluate test-retest reliability. Results Factor analysis demonstrated two (physical and psychological) components for the SBST-TH (39.38% of the total variance). The Cronbach’s alpha (0.86 for total score and 0.76 for psychosocial subscore) represent satisfactory internal consistency. The acceptability of intraclass correlation coefficient was found in the total (0.73) and subscore (0.79). The areas under the curve (AUC) for the total score ranged 0.67–0.85 and 0.66–0.75 for subscore. The excellent discriminative validity was observed (AUC = 0.85, 95% confidence interval = 0.72, 0.97) between the total score of the SBST-TH and disability (RMDQ). Spearman’s correlation coefficients represented moderate to strong correlation (0.32–0.56) between the SBST-TH and all questionnaires. The findings suggest a good relationship between the SBST-TH and disability and quality of life. Owing to the results from the convergent and discriminative validity, construct validity of the SBST-TH can be supported. The minimal detectable changes of the total score and subscore were 2.04 and 1.60, respectively. Significant floor and ceiling effects were not found in the SBST-TH. Conclusion The SBST-TH was successfully translated and adapted. It is a valid and reliable tool to classify Thai patients with non-specific LBP into low, moderate and high risks for chronicity. Trial registration TCTR20191009005 #.

Online testing is critical to ensuring reliable operations of the next generation of supercomputers based on a kilo-core network-on-chip (NoC) interconnection fabric. We present a parallel software-based self-testing (SBST) solution that makes use of the bounded model checking (BMC) technique to generate test sequences and parallel packets. In this method, the parallel SBST with BMC derives the leading sequence for each router’s internal function and detects all functionally- testable faults related to the function. A Monte-Carlo simulation algorithm is then used to search for the approximately optimum configuration of the parallel packets, which guarantees the test quality and minimizes the test cost. Finally, a multi-threading technology is used to ensure that the Monte-Carlo simulation can reach the approximately optimum configuration in a large random space and reduce the generating time of the parallel test. Experimental results show that the proposed method achieves a high fault coverage with a reduced test overhead. Moreover, by performing online testing in the functional mode with SBST, it effectively avoids the over-testing problem caused by functionally untestable turns in kilo-core NoCs.

Software-based test (SBST) techniques are increasingly being used for testing of modern processors because of the ease of synthesis using evolutionary approaches, coverage for difficult to test faults, non-intrusive nature, low hardware overhead, etc. However, the test synthesis time required by SBST is high. In this paper, an advanced SBST technique, termed as Rapid SBST (RSBST) is proposed that reduces the overall test synthesis time by reusing the simulation responses of existing test programs of identical observability. The test codes, developed using the evolutionary process, that produce similar fault simulation results are reused for the fault evaluation. We exploit this reusability to enhance the speed of the test synthesis process. The efficacy of the proposed scheme is demonstrated on a 32-bit MIPS processor and on a minimal configuration of 7-stage SPARC V8 Leon3 soft processor. The traditional SBST synthesis requires 122 hours for the MIPS processor and 142 hours for the Leon3 processor to develop test program sets that cover 93.9% and 92.9% of the behavioral-level faults of these processors, respectively. An existing enhanced greedy-cover method, that also detects the hard-to-test faults, improves the coverage towards 96.3% for the MIPS processor and 95.8% for the Leon3 processor, but this slower test development consumes 168 hours and 172 hours, respectively. In the proposed RSBST scheme, the synthesized test codes achieve an adequate fault coverage of 96.1% for the MIPS processor and 95.5% for the Leon3 processor. This accelerated test pattern generation takes 90 hours and 98 hours for these two processors. So it may be concluded that the proposed RSBST technique speeds up the traditional SBST synthesis by a factor of 1.35 while maintaining the fault coverage above 95.5%. To validate the test quality evaluation using behavioral fault models, a strong correlation (94.8%) between the behavioral faults and gate-level faults of MIPS processor is demonstrated and verified for the proposed RSBST scheme. Also, the simulation responses of the test programs synthesized by RSBST scheme consumes only 14.25% of storage space when compared with the storage consumption of the actual simulation used by the existing test code generation methods.

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-to-detect faults remain unidentified by these autogenerated test programs. Also, these approaches have considered fault models which have low correlation with the gate-level fault models. This paper presents a greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor. Subsequently, the overall coverage is also improved. A selection probability is estimated from the testability properties of the processor components and assigned to every instruction to accelerate the test synthesis. The range of performance and scalability are comprehensively evaluated on a configurable MIPS processor and a full-fledged 7-stage pipeline SPARC V8 Leon3 soft processor using behavioral fault models. The efficacy of our approach was explained by demonstrating the correlation between behavioral faults and gate-level faults of MIPS processor for the proposed scheme. Experimental results show that improved coverages of 96.32% for the MIPS processor and 95.8% for the Leon3 processor are achieved in comparison with the conventional methods, which have about 90% coverage on the average.

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors’ results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly state the fault coverage figures to be achieved with respect to permanent faults. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation exists between the system company and the device provider. However, purely functional test often shows several limitations due to the limited accessibility that it can gain on some input/output signals. This paper proposes a hybrid approach, in which a suitable hardware module is added outside a microcontroller to increase its functional testability during the operational phase. Experimental results gathered on several industrial cases-of-study are reported, showing the feasibility of the method.