Journal Article

HASTI: hardware-assisted functional testing of embedded processors in idle times

Kamran, Arezoo

2019

Overview

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors’ results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

• Publisher: The Institution of Engineering and Technology,John Wiley & Sons, Inc
• Subject: built‐in self test / built‐in self‐test methods / Computer architecture / efficient online testing / embedded core testing / embedded processors / Embedded systems / Field study / Functional testing / Hardware / hardware test components / hardware‐assisted functional testing / HASTI / integrated circuit testing / microprocessor chips / multicore architecture / multiprocessing systems / program testing / SBST / segmented test application / short idle times / software‐based self‐testing / Special Issue: Defect and Fault Tolerance in VLSI and Nanotechnology Systems / test architecture / Test methods / test snippet generation approach / zero performance overhead