Explore the vast range of titles available.

Physically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning. The SRAM-PUF, characterized by its simple structure and ease of implementation in various scenarios, has gained widespread usage. The soft-decision Reed–Muller (RM) code, an error correction code, is commonly employed in these designs. This paper introduces the design of an RM code soft-decision attack algorithm to reveal its potential security risks. To address this problem, we propose a soft-decision SRAM-PUF structure based on the elliptic curve digital signature algorithm (ECDSA). To improve the processing speed of the proposed secure SRAM-PUF, we propose a custom ECDSA scheme. Further, we also propose a universal architecture for the critical operations in ECDSA, elliptic curve scalar multiplication (ECSM), and elliptic curve double scalar multiplication (ECDSM) based on the differential addition chain (DAC). For ECSMs, iterations can be performed directly; for ECDSMs, a two-dimensional DAC is constructed through precomputation, followed by iterations. Moreover, due to the high similarity of ECSM and ECDSM data paths, this universal architecture saves hardware resources. Our design is implemented on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) using a Xilinx Virtex-7 and an TSMC 40 nm process. Compared to existing research, our design exhibits a lower bit error rate (2.7×10−10) and better area–time performance (3902 slices, 6.615 μs ECDSM latency).

As elliptic curve cryptography is one of the popular ways of constructing an encoding and decoding processes, public-key algorithms as its basis provide people a comfortable way of exchanging pieces of encoded information. As the time goes by, a lot of algorithms have emerged, some of them are still in use today; some others are still being developed into new forms. The main point of algorithm innovation is to reduce the number of processed operations during every possible step to find maximum efficiency and highest speed while performing the calculations. This article describes an improved method of the López-Dahab-Montgomery (LD-Montgomery) scalar point multiplication in terms of working with binary elliptic curves. It is shown in the article that the possible improvement lies in reordering the set of operations which is used in LD-Montgomery scalar point multiplication algorithm. The algorithm is used to compute point multiplication results of the curves over binary Galois Fields featuring the following m values: . The article also presents the experimental results based on different scalars.

Elliptic curve cryptography (ECC) is widely acknowledged as a method for implementing public key cryptography on devices with limited resources thanks to its use of small keys. A crucial and complex operation in ECC calculations is scalar point multiplication. To improve its execution time and computational complexity in low-power devices, such as embedded systems, several algorithms have been suggested for scalar point multiplication, with each featuring different techniques and mathematical formulas. In this research, we focused on combining some techniques to produce a scalar point multiplication algorithm for elliptic curves over finite fields. The employed methodology involved mathematical analysis to investigate commonly used point multiplication methods. The aim was to propose an efficient algorithm that combined the best computational techniques, resulting in lower computational requirements. The findings show that the proposed method can overcome certain implementation issues found in other multiplication algorithms. In certain scenarios, the proposed method offers a more efficient approach by reducing the number of point doubling and point addition operations on elliptic curves using the inverse of the targeted point.

Elliptic curve cryptography (ECC) is most widely used asymmetric cryptography technique used in the modern engineering applications. This article proposes efficient hardware implementations scalar multiplication of Lopez–Dahab projective co-ordinate based ECC in the platforms of application specific integrated circuit (ASIC) and field programmable gate array logic (FPGA). The configurable G F ( 2 163 ) arithmetic unit is used to design the proposed scalar multiplication in ASIC platform with 45  nm CMOS technology. The scalar multiplication includes point addition and doubling. Since the G F ( 2 163 ) operations such as addition, multiplication, fused multiply addition (FMA), and multiplicative inverse required in the point addition and doubling are performed using the configurable G F ( 2 163 ) arithmetic unit, area and power dissipation of the proposed scalar multiplication in the ASIC platform is less than various existing designs. Similarly, both the Cortex-A9 cores of Zynq 7000 system on chip (SoC) are used to perform the two scalar multiplications in parallel, where the first core performs the point addition of the scalar multiplication while the second core performs the point doubling. Here, both the cores control separate co-processors to perform the point addition or doubling. Due to this dual core implementation in FPGA, the throughput of the proposed scalar multiplication in FPGA is greater than various existing designs.

Reducing the computation time of scalar multiplication for elliptic curve cryptography is a significant challenge. This study proposes an efficient scalar multiplication method for elliptic curves over finite fields GF(2m). The proposed method first converts the scalar into a binary number. Then, using Horner’s rule, the binary number is divided into fixed-length bit-words. Each bit-word undergoes repeating point doubling, which can be precomputed. However, repeating point doubling typically involves numerous inverse operations. To address this, significant effort has been made to develop formulas that minimize the number of inverse operations. With the proposed formula, regardless of how many times the operation is repeated, only a single inverse operation is required. Over GF(2m), the proposed method for scalar multiplication outperforms the sliding window method, which is currently regarded as the fastest available. However, the introduced formulas require more multiplications, squares, and additions. To reduce these operations, we further optimize the square operations; however, this introduces a trade-off between computation time and memory size. These challenges are key areas for future improvement.

Ciphertext-Policy Attribute-Based Encryption (CP-ABE) technology provides a new solution to address the security and fine-grained access control of traffic information in vehicular ad hoc networks (VANETs). However, in most CP-ABE schemes for VANETs, attribute revocation suffers from high system consumption and complex revocation operations, as well as from high computational overhead and low efficiency due to the use of bilinear pairwise operations. Based on this, this paper proposes a lightweight CP-ABE scheme that supports direct attribute revocation in VANETs. The scheme implements an agent-based direct attribute revocation mechanism by separating dynamic and static attributes of vehicle terminals, which reduces system consumption and simplifies the revocation operation process. The scheme uses scalar multiplication on elliptic curves instead of bilinear pairing operations and uses computational outsourcing techniques to reduce the terminal decryption cost and improve the efficiency of the scheme. The security and performance analysis shows that the overall efficiency of our scheme is better than the existing schemes under the premise of ensuring data confidentiality and integrity.

In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 μm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.

The cone of lower semicontinuous traces is studied with a view to its use as an invariant. Its properties include compactness, Hausdorffness, and continuity with respect to inductive limits. A suitable notion of dual cone is given. The cone of lower semicontinuous 2-quasitraces on a (non-exact) C*-algebra is considered as well. These results are applied to the study of the Cuntz semigroup. It is shown that if a C*-algebra absorbs the Jiang-Su algebra, then the subsemigroup of its Cuntz semigroup consisting of the purely non-compact elements is isomorphic to the dual cone of the cone of lower semicontinuous 2-quasitraces. This yields a computation of the Cuntz semigroup for the following two classes of C*-algebras: C*-algebras that absorb the Jiang-Su algebra and have no non-zero simple subquotients, and simple C*-algebras that absorb the Jiang-Su algebra.

With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in ECC. Based on this background information, we propose our own research objectives. In this paper, a low-latency and low-area ECSM architecture based on the comb algorithm is proposed. The detailed methodology is as follows. The recoding-k algorithm and randomization-Z algorithm are used to improve security, which can resist sample power analysis (SPA) and differential power analysis (DPA). A low-area multi-functional architecture for comb is proposed, which takes into account different stages of the comb algorithm. Based on this, the data dependency is considered and the comb architecture is optimized to achieve a uniform and efficient execution pattern. The interleaved modular multiplication algorithm and modified binary inverse algorithm are used to achieve short clock cycle delay and high frequency while taking into account the need for a low area. The proposed architecture has been implemented on Xilinx Virtex-7 series FPGA to perform ECSM on 256-bits prime field GF(p). In the hardware architecture with only 7351 slices of resource usage, a single ECSM only takes 0.74 ms, resulting in an area-time product (ATP) of 5.41. The implementation results show that our design can compete with the existing state-of-the-art engineering in terms of performance and has higher security. Our design is suitable for computing scenarios where security and computing speed are required. The implementation of the overall architecture is of great significance and inspiration to the research community.