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Reliable characterization techniques that guarantee real‐time quality control with a non‐destructive and multiscale approach are currently an essential necessity for electronic industries. Tip‐Enhanced Raman Spectroscopy (TERS) offers an excellent solution to this demand. In addition to providing chemical composition through the Raman spectrometer, TERS leverages the high lateral resolution of the coupled Atomic Force Microscope, enabling chemical and morphological characterization of samples down to the nanometer scale. This study advances the application of TERS by employing ad‐hoc prepared TiN‐coated probes, engineered to operate in cleanrooms while guaranteeing remarkable performances in terms of electromagnetic field enhancement. The subject of this analysis is a strained‐silicon‐based device, a technology meant to enhance the carrier's mobility in Complementary Metal‐Oxide‐Semiconductor (CMOS) architectures. The goal of the characterization is to detect the strain induced by a thin Si1‐xGex alloy grown on a Si(100) substrate in the silicon lattice. TERS enables not only the detection of strain in the crystal structure but also its magnitude at different levels of depth, despite the penetration depth of the laser employed. This study is a result of the activities carried out in the framework of the European Union founded project CHALLENGES included in the Horizon2020 program. This paper demonstrates how Tip‐Enhanced Raman Spectroscopy (TERS) can detect diverse levels of strain in a SiGe‐Si structure in less than 20 nm of depth with lateral resolution under 100 nm. The measures are performed with a TiN‐coated probe, which secures a remarkable enhancement of the optical signal, while being chemically stable to allow TERS to operate in cleanroom.

This paper aims at the investigation of acoustic streaming produced by surface acoustic waves (SAWs) in a drop. Computational simulation of acoustofluidic phenomenon, using lattice Boltzmann method (LBM), presenting acoustic applications in flow control, and a relatively complete parametric study are the motivations of this work. For this purpose, a computational fluid dynamics modeling based on multi-relaxation time multi-component multiphase color gradient lattice Boltzmann method was used. The simulations were carried out at wave frequencies ranging from 20 MHz to 271 MHz and wave amplitudes ranging from 0.5 nm to about 350 nm. First, the non-dimensional form of Navier-Stokes equations based on this phenomenon is presented in this work and the physics of flow is explained. Then, the consistency of the model and experimental observations is considered and our numerical results pass the physical reals. Based on our results, comparison between Lithium Niobate and Zinc Oxide Silicon devices shows that in the pumping mode, the wet length of drop on Zinc Oxide material is shorter about 10%. Also, drop moves faster on the Zinc Oxide Silicon device (about 20% in 64.5 MHz and 350 nm). Moreover, in the jetting mode, drop is detached, from Zinc Oxide Silicon device, in about 70% shorter time duration. The findings indicate that in the jetting mode a counter rotating vortex pair is formed near the drop, while the vortices are stronger for Zinc Oxide Silicon device. So, in the liquid transport applications, Zinc Oxide Silicon device is more suitable. Other important results which are presented in this work are about the non-dimensional parameters and their ranges in these phenomena. The most important non-dimensional parameters governing the physics of problem are identified. Additionally, the ranges of different physical modes (based on non-dimensional parameters) are determined, using numerical results and experimental data. The results show that in the pumping mode, Reynolds, Weber, and capillary numbers are between 3 and 1400, 10−5-0.02, and 4 × 10−5-2.5 × 10−3, respectively. Also, in the jetting mode, the mentioned parameters are between 757 and 4600, 0.008–0.3, and 0.001–0.006, respectively.

On a scalable silicon technology platform, we demonstrate photodetectors matching or even surpassing state-of-the-art III–V devices. As key components in high-speed optoelectronics, photodetectors with bandwidths greater than 100 GHz have been a topic of intense research for several decades. Solely InP-based detectors could satisfy the highest performance specifications. Devices based on other materials, such as germanium-on-silicon devices, used to lag behind in speed, but enabled complex photonic integrated circuits and co-integration with silicon electronics. Here we demonstrate waveguide-coupled germanium photodiodes with optoelectrical 3-dB bandwidths of 265 GHz and 240 GHz at a photocurrent of 1 mA. This outstanding performance is achieved by a novel device concept in which a germanium fin is sandwiched between complementary in situ-doped silicon layers. Our photodetectors show internal responsivities of 0.3 A W−1 (265 GHz) and 0.45 A W−1 (240 GHz) at a wavelength of 1,550 nm. The internal bandwidth–efficiency product of the latter device is 86 GHz. Low dark currents of 100–200 nA are obtained from these ultra-fast photodetectors.By sandwiching a germanium fin between complementary in situ-doped silicon layers, a waveguide-coupled germanium photodiode with a 3-dB bandwidth of 265 GHz, accompanied by high responsivity and low dark current, is realized.

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2  V −1  s −1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics. Monolayer MoS 2 is grown at the back end of the line of 200 mm silicon CMOS wafers at a temperature of <300 °C, and hybrid silicon CMOS/MoS 2 circuits are demonstrated through heterogeneous integration.

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays.

A two-qubit quantum processor in a silicon device is demonstrated, which can perform the Deutsch–Josza algorithm and the Grover search algorithm. Taken for a spin in silicon The development of platforms for spin-based quantum computing continues apace. The individual components of such a system have been the subject of much investigation, and they have been assembled to implement specific quantum-computational algorithms. Thomas Watson and colleagues have now taken such component integration and control to the next level. Using two single-electron-spin qubits in a silicon-based double quantum dot, they realize a system that can be simply programmed to perform different quantum algorithms on demand. Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing 1 , 2 . In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform 3 , 4 , 5 . Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations 6 , 7 , 8 , 9 . However, as seen with small-scale demonstrations of quantum computers using other types of qubit 10 , 11 , 12 , 13 , combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. Here we overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

Photonic qubits should be controllable on-chip and noise-tolerant when transmitted over optical networks for practical applications. Furthermore, qubit sources should be programmable and have high brightness to be useful for quantum algorithms and grant resilience to losses. However, widespread encoding schemes only combine at most two of these properties. Here, we overcome this hurdle by demonstrating a programmable silicon nano-photonic chip generating frequency-bin entangled photons, an encoding scheme compatible with long-range transmission over optical links. The emitted quantum states can be manipulated using existing telecommunication components, including active devices that can be integrated in silicon photonics. As a demonstration, we show our chip can be programmed to generate the four computational basis states, and the four maximally-entangled Bell states, of a two-qubits system. Our device combines all the key properties of on-chip state reconfigurability and dense integration, while ensuring high brightness, fidelity, and purity. Frequency-bin qubits get the best of time-bin and dual-rail encodings, but require external modulators and pulse shapers to build arbitrary states. Here, instead, the authors work directly on-chip by controlling the interference of biphoton amplitudes generated in multiple, coherently-pumped ring resonators.

Phase flicker has become an important performance parameter for the liquid crystal on silicon (LCOS) devices. Since the phase response of the LCOS device cannot be measured directly, it is usually derived from the intensity response of the modulated light beam when the LCOS device was placed between a pair of crossed polarisers. However, the relationship between the intensity of the beam and the phase response of the LCOS device is periodic. This would lead to uncertainty in the phase flicker measurement. This paper analyses this measurement uncertainty through both simulation and experiments. It also proposed a strategy to minimise the uncertainty.

Single-photon detection has emerged as a method of choice for ultra-sensitive measurements of picosecond optical transients. In the short-wave infrared, semiconductor-based single-photon detectors typically exhibit relatively poor performance compared with all-silicon devices operating at shorter wavelengths. Here we show a new generation of planar germanium-on-silicon (Ge-on-Si) single-photon avalanche diode (SPAD) detectors for short-wave infrared operation. This planar geometry has enabled a significant step-change in performance, demonstrating single-photon detection efficiency of 38% at 125 K at a wavelength of 1310 nm, and a fifty-fold improvement in noise equivalent power compared with optimised mesa geometry SPADs. In comparison with InGaAs/InP devices, Ge-on-Si SPADs exhibit considerably reduced afterpulsing effects. These results, utilising the inexpensive Ge-on-Si platform, provide a route towards large arrays of efficient, high data rate Ge-on-Si SPADs for use in eye-safe automotive LIDAR and future quantum technology applications. By incorporating germanium, single-photon avalanche diode detectors using silicon-based platforms are applied to infrared light detection. Here, a cost-effective planar detector geometry is presented yielding high detection efficiency suitable for applications such as sparse photon imaging or LIDAR.

Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass associated with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses while performing high-frequency reflectometry off one gate electrode, we perform single-electron operations within the array that demonstrate single-shot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the two-dimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutation-based quantum algorithms. Semiconductor spin-qubits with CMOS compatible architectures could benefit from the industrial capacity of the semiconductor industry. Here, the authors make the first steps in demonstrating this by showing single electron operations within a two-dimensional array of foundry-fabricated quantum dots.