Explore the vast range of titles available.

Large language models (LLMs) have shown increasing potential in analogue circuit analysis automation, yet their ability to understand and identify functional blocks can vary significantly depending on the representation format of the circuit. This paper investigates how circuit representation, flat SPICE Netlists versus structured PySpice code, influences LLM performance in functional block recognition tasks. Using a benchmark of ten analogue comparator circuits derived from a standard educational collection, we evaluate five state‐of‐the‐art LLMs across both representations. Each circuit is annotated with ground‐truth sub‐topologies, and models are prompted to extract these blocks in a standardized JSON format. Our results reveal that DeepSeek R1 achieves the highest average accuracy on Netlist inputs, while GPT 5 provides the most balanced performance across both formats. LLaMA 4 shows a slight advantage on PySpice compared to Netlist, indicating that semantic cues in structured code can benefit certain models. Overall, most models still perform better on Netlist than on PySpice, demonstrating that code‐structured representations do not generically improve performance and highlighting the importance of representation format selection in LLM‐driven electronic design automation.

High step‐down DC‐DC converters require a robust and low power pre‐regulated supply for bandgap reference. This paper proposes a structure that comprised of two current paths to achieve energy efficient pre‐regulation under high and low input voltage conditions. The design eliminated large size resistors for current limiting which is usually required for high input supplies. The presented pre‐regulator structure combined with the bandgap circuit was realized with the TSMC 180‐nm BCD process. The measured results show the proposed structure has a wide input voltage range of 3.5–45 V, a temperature coefficient of 5.63 ppm/°C and typical average current consumption of 1.1 μA. This paper proposed a dual‐channel pre‐regulation structure for the bandgaps, which is suitable for the high step‐down DC‐DC convertors with low quiescent current and small area requirement.

This letter introduces a 7‐bit, 700 MS/s, 2b/cycle asynchronous successive approximation register (SAR) analogue‐to‐digital converter (ADC). To relax the settling requirement, the capacitive digital‐to‐analogue converter (CDAC) is designed with non‐binary weighting to provide redundancy, implemented using a pre‐charge reduction scheme that removes next‐cycle pre‐charge activity in a 2b/cycle SAR ADC. To reduce the area of this non‐binary weighted CDAC, a partially merged capacitor switching scheme is proposed. The prototype ADC is fabricated in a 28 nm CMOS process with an active die area of 0.0077 mm2. At a 700 MS/s sampling rate, the ADC achieves a signal‐to‐noise‐and‐distortion ratio of 37.6 dB and a spurious‐free dynamic range of 49.1 dB at the Nyquist input frequency. The power consumption is 2.41 mW from a 1.0 V supply, resulting in a Walden figure of merit of 55.56 fJ/conversion step at Nyquist. This letter presents a 7‐bit asynchronous successive approximation register analogue‐to‐digital converter operating at 700 MS/s with a 2b/cycle conversion scheme, incorporating a partially merged capacitor switching (PMCS). By applying PMCS to the non‐binary weighted capacitive digital‐to‐analogue converter (CDAC), the number of unit capacitors is effectively reduced, contributing to a smaller CDAC area.

In this paper, a current‐mode loser‐take‐all (LTA) circuit is proposed. The proposed circuit has a high input dynamic range and offers very high precision. The circuit maintains high precision not only at low currents close to zero but also at currents in the range of several hundred microamperes. Additionally, the power consumption per cell in the proposed circuit is very low. The circuit is designed using 180 nm technology, operating at a supply voltage of 1.8 V, with a power consumption of 18 µW per cell in a 3‐input structure. In the proposed circuit, the maximum error occurs at an input range of 200 µA and an input frequency of 2 MHz, which is 1.3%. This letter a novel current‐mode loser‐take‐all circuit for a wide range of inputs. The proposed circuit has been designed and simulated in 180 nm CMOS technology. The results confirm that the maximum error has been reduced over a wide range of input comparing the other similar works.

This paper proposes a novel bandgap voltage reference (BGR) with low temperature coefficient, ultra‐low noise and without start‐up circuit. Designed in a TSMC 180‐nm CMOS technology, this bandgap voltage reference operates in the temperature range of −55 to 125°C with 5‐V voltage supply and provides a 1.2‐V output voltage VBG. A 16.8 ppm/°C temperature coefficient (TC) and the output RMS noise from 0.1 to 10 Hz of 1.69 µV is achieved. The circuit‐level simulation results verify the presented structure. By the improved architecture of the IPTAT generation stage, the proposed BGR can be powered on normally without designing additional start‐up circuit to eliminate equilibrium point, which greatly simplifies the circuit complexity. This paper proposes an ultra‐low noise bandgap voltage reference without start‐up circuit.

This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design. This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies.

Incipient faults in analogue circuits used in complex electrical systems are hard to diagnose due to weak fault features. To improve the reliability and maintainability of analogue circuits in complex electrical systems, a novel incipient soft fault diagnosis method for analogue circuits based on a multilayer dictionary learning and coding network is proposed, including feature preprocessing, linear dictionary feature encoding, and classification modules. In the first module, time–frequency analyses are performed using continuous wavelet transforms to demonstrate the spectrum maps of the fault signals, while scale-invariant feature transforms are used to enhance local features and obtain the keypoint descriptors of the time–frequency spectrum. In the second module, fault features are obtained by locally constrained linear coding (LLC) method using complete dictionaries from the keypoint descriptors acquired in the previous module, which are captured by linear combination of several adjacent atoms in the dictionary learning. To address the limitations of single-layer dictionary learning methods in complete extraction of fault features, a multilayer learning method is used to get richer fault information and improve the diagnosis accuracy. Finally, the linear output features are captured through pooling and fully connected layers. In the third module, the linear features acquired in the second module are quickly classified with simple linear classifiers. The experimental results demonstrate that the proposed method outperforms existing fault diagnosis methods. In order to verify the effectiveness of the proposed method in analogue circuit fault diagnosis, the Sallen–Key filter circuit and four-op-amp biquadratic filter circuit, which are widely used in the field, are selected as experimental circuits in this paper. Specifically, when the component fault values are offset by 20% of their nominal value, the proposed method achieves accuracies of 99.20% for the Sallen–Key bandpass filter circuit and 98.48% for the four-op-amp biquadratic filter circuit.

This letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve a temperature coefficient (TC) of 2.23 ppm/°C. Unlike traditional BGRs, the unique folding compensation method of this circuit improves the performance at low temperature and can also be applied within a specific temperature range. This letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve temperature coefficient (TC) of 2.23 ppm/°C.

Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented. The DCMLC breaks the trade‐off between settling time and regeneration time in traditional CML comparator design by utilizing dynamic logic and separately optimizes the tracking stage and regeneration stage for a correct latch operation at ultrahigh speed. Compared with the traditional CML comparator, the DCMLC reduces delay by 36% and has better input sensitivity on high baud rates at the cost of 7% shrunk output swing. The negative capacitance is adopted to achieve a 0.5 dB bandwidth extension ratio of up to 1.89. The reduced delay and wider bandwidth of the proposed comparator allow the implementation of 4‐tap direct DFE at 56 Gbps with 2.8 pJ/bit energy efficiency and an active area of 0.007 mm2 in 65‐nm CMOS technology.

This paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12‐bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9‐μV input referred noise (IRN), 10.8‐effective number of bits (ENOB), 37.8‐μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18‐μm CMOS process and validated by in‐vivo experiment on a lab mouse with a 36‐channel silicon‐based neural probe. A 36‐channel neural recording ASIC is designed and implemented in this letter. The proposed ASIC uses modular digital pixel (MDP) technique to improve the expandability and robustness by eliminating long routing of sensitive analog signals on chip and can be easily expanded to high‐channel‐count application without re‐design of analog circuit.