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This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.

This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design. This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies.

A new quadratic boost converter is presented in this study. Compared with the conventional quadratic boost converter, the proposed converter has the feature of lower buffer capacitor voltage stress. This advantage is very valuable for high voltage and high-voltage gain applications. The proposed converter also employed only one active switch and two LC (inductor-capacitor) filters. Detailed analysis for its continuous current mode operation and discontinuous current mode operation both are presented. In addition, modelling for the proposed converter is also developed in this study. A prototype circuit is built and the experimental results confirm the feasibility and performance of the high step-up converter.

This paper presents a novel buck converter with dual-loop control technology, which does not need to detect the inductor current directly. The structure of the control loops is easy to implement, one loop controls the output voltage, and the other controls the switching frequency. With the dual loops control mechanism, the output voltage and switching frequency can be accurately controlled only by measuring the output and input voltage, without sensing the inductor current. The buck converter can generate an output voltage of 1.0–2.5 V when the input voltage and load current are 3.0–3.6 V and 100–500 mA, respectively. The design was verified by SIMPLIS. The simulation results show that the switching frequency variation is less than 1% at the output voltage of 1.0–2.5 V. The recovery time is less than 1.5 μs during the load change. The circuit can be fabricated by using the TSMC 0.35μm 2P4M CMOS processes. The control scheme, theoretical analysis and circuit implementation are presented in this paper.

In this paper, a new control scheme for buck converters was proposed. The buck converter utilizes the dual control loop to improve transient response and has the constant switching frequency. The control scheme is mainly as follows: (a) The switch-ON time is regulated by the constant frequency mechanism. (b) The switch-OFF time is regulated by the output voltage. The spec/features of the proposed converter are listed as: (1) The buck converter has an output of 1.0–2.5 V for the input of 3.0–3.6 V. The load current ranges from 100 mA to 500 mA. (2) The actual current sensor is not required. (3) The simulation results show that the recovery time is less than 1.6 μs during load changes. (4) The variation in switching frequency is smaller than 1.05% over the output range of 1.0–2.5 V. (5) This circuit can be fabricated in future by UMC 0.18 μm 1P6M CMOS processes. This paper depicts the control scheme, theoretical analysis, and implementation.

Abstract Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current‐mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large‐signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage.

The Renewable energy system, electric vehicle, and telecommunication applications require relatively stable power converters with a high gain and enhanced noise immunity. A study of three different types of current-mode controllers for high-gain ultra-lift Luo-converter (ULC) is discussed in this paper. The stability of a constant frequency peak current-mode controller (PCM), an average current-mode controller (ACM) and a variable frequency hysteresis current-mode controller (HCM) are analyzed based on small-signal characteristics. Using mathematical modeling of the controllers, the closed-loop transfer functions such as control voltage to output voltage, current loop gain, inductor current to control voltage, and audio susceptibility are obtained. These transfer functions along with MATLAB simulation results for PCM, ACM and HCM controllers are compared. Then, the component losses of the ULC converter using PCM, ACM and HCM controllers are calculated and an efficiency comparison of different control techniques is done. Investigations of the voltage and current stresses of the switch and diodes are also carried out. Finally, a prototype is fabricated to validate the performance of the converter.

This article realizes a novel design for a first-order current-mode multifunction filter with many outputs and a single input. One dual-X second-generation multioutput current conveyor (DX-MOCCII) is the one active building block in the proposed filter circuit. A single capacitor and an NMOS transistor working in the linear region are the only externally employed passive components. By acting as a linear resistor, nMOS transistors require a smaller area than traditional resistors and allow the design of tunable current mode filter circuits. The realized current-mode filter provides one high-pass, one all-pass, and two low-pass responses at different outputs. The pole frequency of the first-order filter circuit can be adjusted considerably using an NMOS transistor. The theoretical conclusions are validated using the PSPICE program simulator and the 0.18 µm CMOS process parameters.

This paper introduces a novel direct current to direct current (DC-DC) buck converter that uses a pseudo-current hysteresis controller and an on-chip soft start circuit for improved transient performance in automotive applications. The proposed converter, implemented with Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) one-poly-six-metal (1P6M) technology, includes a rail-to-rail current detection circuit and an on-chip soft start circuit to handle transient responses and improve efficiency. Transient response analysis shows fast settling times of 28 µs for both load current changes from 100 mA to 1 A and reversals with consistent transient voltages of approximately 190 mV and peak power efficiency of 99.32% at 5 V output voltage and 100 mA load current. Additionally, the converter maintains a constant output voltage of approximately 5 V across the entire load current range with an average accuracy of 90.41%. A comparative analysis with previous work shows superior performance in terms of figure of merit (FOM). Overall, the proposed pseudo-current hysteresis controlled buck converter exhibits remarkable transient response, load regulation and power efficiency, positioning it as a promising solution for demanding applications, particularly in automotive systems where precise voltage regulation is crucial.

An innovative Synchronous Buck Converter (SBC) with a wide input voltage range is presented in this article for use in Electric Vehicle (EV) applications. The disadvantages of higher losses in an Asynchronous Buck Converter (ABC) are intended to be addressed by the Synchronous Buck Converter. Fewer losses occur in the circuit when MOSFET (or any controlled switch) is used in place of diode. To enhance system performance, the control approach known as Emulated Peak Current Mode (EPCM) is employed. The design of a broad range input SBC and the investigation of power loss calculations using different control techniques, which are implemented using PSIM, are the primary contributions made in this paper. The buck converter employed in this paper has an output voltage of 12 V and a wider input voltage range of 40â75 V. It is utilized by electric vehicles' light and horn systems. Using PSIM software, the SBC using the EPCM, Current Mode Control (CMC), and Voltage Mode Control (VMC) techniques is simulated. Hardware results coincide with the simulation results and thus the results are validated.