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In high performance computing systems and signal processing, there is a basic set of mathematical functions that are essential. While addition, subtraction and multiplication are well understood, there is less literature on square-rooting, which is a particularly time- and resource-consuming function. Traditional non-restoring algorithms produce a mantissa half the length of the input mantissa, causing a loss of precision. This study presents a method for increasing the accuracy of this algorithm. It is shown to work for all IEEE-754R standard floating-point numbers. Error analysis shows a 57-fold (for half-precision) and 134e6-fold improvement (for double-precision) in the normalised error, equivalent to at most 1 Units of Least Precision. Resource and performance optimised variants are analysed and their throughput analysed. On an Intel Stratix V device, performance optimised implementations achieve a throughput of 717 MFLOPs. Resource optimised implementations on a low-cost device require only 127 Adaptive Logic Modules and 232 registers, with a throughput of 8.56 MFLOPs. All implementations are DSP block and memory free, saving valuable resources. The maximum throughput of the presented design is 15.5 times greater than that proposed by Pimentel et al. and two orders of magnitude greater than typical multiply-accumulate methods.

PurposeIn today’s uncertain business environment, Industry 4.0 is regarded as a viable strategic plan for addressing a wide range of manufacturing-related challenges. However, it appears that its level of adoption varies across many countries. In the case of a developing economy like India, practitioners are still in the early stages of implementation. The implementation of Industry 4.0 appears to be complex, and it must be investigated holistically in order to gain a better understanding of it. Therefore, an attempt has been made to examine the Industry 4.0 implementation for the Indian manufacturing organization in a detailed way by analyzing the complexities of relevant variables.Design/methodology/approachSAP-LAP (situation-actor-process and learning-action-performance) and an efficient interpretive ranking process (e-IRP) were used to analyze the various variables influencing Industry 4.0 implementation. The variables were identified, as per SAP-LAP, through a thorough review of the literature and based on the perspectives of various experts. The e-IRP has been used to prioritize the selected elements (i.e. actors with respect to processes and actions with respect to performance) of SAP-LAP.FindingsThis study ranked five stakeholders according to their priority in Industry 4.0 implementation: government policymakers, industry associations, research and academic institutions, manufacturers and customers. In addition, the study also prioritized important actions that need to be taken by these stakeholders.Practical implicationsThe results of this study would be useful in identifying and managing the various actors and actions related to Industry 4.0 implementation. Accordingly, their prioritized sequence would be useful to the practitioners in preparing the well-defined and comprehensive strategic roadmap for Industry 4.0.Originality/valueThis study has adopted qualitative and quantitative approaches for identifying and prioritizing different variables of Industry 4.0 implementation. This, in turn, helps the stakeholder to comprehend the concept of Industry 4.0 in a much simpler way.

Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

This work presents the results of a research study focused on the development and evaluation of an algorithmic optimal control framework for energy-efficient operation of screw compressors in smart power systems. The proposed approach is based on the Pontryagin maximum principle (PMP), which enables the synthesis of a mathematically grounded regulator that minimizes the total energy consumption of a nonlinear electromechanical system composed of a screw compressor and a variable-frequency induction motor. Unlike conventional PID controllers, the developed algorithm explicitly incorporates system constraints, nonlinear dynamics, and performance trade-offs into the control law, allowing for improved adaptability and energy-aware operation. Simulation results obtained using MATLAB/Simulink confirm that the PMP-based regulator outperforms classical PID solutions in both transient and steady-state regimes. Experimental tests conducted in accordance with standard energy consumption evaluation methods showed that the proposed PMP-based controller provides a reduction in specific energy consumption of up to 18% under dynamic load conditions compared to a well-tuned basic PID controller, while maintaining high control accuracy, faster settling, and complete suppression of overshoot under external disturbances. The control system demonstrates robustness to parametric uncertainty and load variability, maintaining a statistical pressure error below 0.2%. The regulator’s structure is compatible with real-time execution on industrial programmable logic controllers (PLCs), supporting integration into intelligent automation systems and smart grid infrastructures. The discrete-time PLC implementation of the regulator requires only 103 arithmetic operations per cycle and less than 102 kB of RAM for state, buffers, and logging, making it suitable for mid-range industrial controllers under 2–10 ms task cycles. Fault-tolerance is ensured via range and rate-of-change checks, residual-based plausibility tests, and safe fallbacks (baseline PID or torque-limited speed hold) in case of sensor faults. Furthermore, the proposed approach lays the groundwork for hybrid extensions combining model-based control with AI-driven optimization and learning mechanisms, including reinforcement learning, surrogate modeling, and digital twins. These enhancements open pathways toward predictive, self-adaptive compressor control with embedded energy optimization. The research outcomes contribute to the broader field of algorithmic control in power electronics, offering a scalable and analytically justified alternative to heuristic and empirical tuning approaches commonly used in industry. The results highlight the potential of advanced control algorithms to enhance the efficiency, stability, and intelligence of energy-intensive components within the context of Industry 4.0 and sustainable energy systems.

A primary challenge in isogeny-based cryptography lies in the substantial computational cost associated to computing and evaluating prime-degree isogenies. This computation traditionally relied on Vélu’s formulas, an approach with time complexity linear in the degree but which was further enhanced by Bernstein, De Feo, Leroux, and Smith to a square-root complexity. The improved square-root Vélu’s formulas exhibit a degree of parallelizability that has not been exploited in major implementations. In this study, we introduce a theoretical framework for parallelizing isogeny computations and provide a proof-of-concept implementation in C with OpenMP. While the parallelization effectiveness exhibits diminishing returns with the number of cores, we still obtain strong results when using a small number of cores. Concretely, our implementation shows that for large degrees it is easy to achieve speedup factors of up to 1.74, 2.54, and 3.44 for two, four, and eight cores, respectively.

Traditionally, the usual multipliers are used to multiply signals by a constant, but multiplication by a constant can be considered as a special operation requiring the development of specialized multipliers. Different methods are being developed to accelerate multiplications. A large list of methods implement multiplication on a group of bits. The most known one is Booth’s algorithm, which implements two-digit multiplication. We propose a modification of the algorithm for the multiplication by three digits at the same time. This solution reduces the number of partial products and accelerates the operation of the multiplier. The paper presents the results of a comparative analysis of the characteristics of Booth’s algorithm and the proposed algorithm. Additionally, a comparison with built-in FPGA multipliers is illustrated.

This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal of this study is to design a high throughput and FPGA efficiency (FPGA-Eff) cryptosystem for high-traffic applications. To achieve high throughput, loop-unrolling, inner and outer pipelining techniques are employed. In AES, substitution bytes (Sub-Bytes) is one of the costly functions that occupy a large number of resources and has a large delay. To reduce the area of Sub-Bytes, new-affine-transformation, which is the combination of inverse isomorphic and affine transformation, is proposed and employed. Besides that, AES has been modified according to the proposed architecture. For the first nine rounds, Shift-Rows and Sub-Bytes have been exchanged, and Shift-Rows is merged with Add-Round-Key. To make an equal latency between stages, Mix-Columns is divided into two different stages. AES is implemented in counter mode on Xilinx Virtex-5 using VHDL. The proposed implementation achieves a throughput of 79.7 Gbps, FPGA-Eff of 13.3 Mbps/slice, and frequency of 622.4 MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%.

This research investigates the impact of strategic management practices on the performance of small and medium-sized enterprises (SMEs) in the Abidjan Metropolis of the Ivory Coast. Strategic management involves how managers define an organization's long-term direction, establish specific performance objectives, and create strategies to reach them. Strategic planning ensures alignment between an organization's goals, resources, and changing opportunities. This study utilized Strategy Evaluation and Monitoring (SEM) to assess the impact of strategic management practices on SMEs in the Abidjan Metropolitan Area, focusing on the Resource-Based View (RBV) as a strategic management tool, which has received limited attention in SEM research. Data were collected from 300 small and medium-sized enterprises (SMEs) operating in Abidjan using a descriptive cross-sectional design, capturing various details such as gender, age, education level, job position, employee count, experience, and type of organization. Findings indicate that while strategic planning had a negative impact on financial performance, it positively influenced non-financial success. The study also revealed that strategy design has a positive impact on both the financial and non-financial performance of SMEs. Conversely, there was no significant effect on the financial results of the SMEs following the implementation of their plans, and a notable negative impact on non-financial performance was identified during the execution of the strategy. Additionally, strategic review and monitoring were found to have a significant influence on the non-financial performance of SMEs in the Abidjan area. Overall, the results suggest that a competitive advantage positively affects the performance of SMEs, offering important insights into the Resource-Based View (RBV), which highlights that human and social capital resources are crucial success factors for SMEs in times of uncertainty. These insights can significantly aid strategic managers in enhancing their small and medium-sized enterprises '(SMEs') standing in emerging markets during challenging periods.

This study aims to investigate the application and management strategies of ChatGPT in financial services. We explore the potential of ChatGPT in financial customer service, financial planning, risk management, portfolio analysis, insurance services, and fraud prevention, for which it is found to provide efficient automated solutions for financial institutions. To successfully implement ChatGPT applications, we emphasize the importance of managing conversational AI, including clarifying business requirements, identifying application scenarios, building appropriate data models, ensuring security and privacy, performing manual supervision, and establishing evaluation and feedback mechanisms. Besides, we also analyze the challenges and limitations of ChatGPT in financial business, such as data trustworthiness, data privacy and security issues, model bias, and regulatory and compliance issues. Under this foundation, we propose corresponding solutions. Finally, we look forward to the future development of ChatGPT in the financial domain and make corresponding practical suggestions to help financial institutions better utilize ChatGPT technology.

Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers. We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice. Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor.