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Multispectral filter array (MSFA)-based imaging is a compact, practical technique for snapshot spectral image capturing and reconstruction. The imaging and reconstruction quality is highly influenced by the spectral sensitivities and spatial arrangement of channels on MSFAs, and the used reconstruction method. In order to design a MSFA with high imaging capacity, we propose a sparse representation based approach to optimize spectral sensitivities and spatial arrangement of MSFAs. The proposed approach first overall models the various errors associated with spectral reconstruction, and then uses a global heuristic searching method to optimize MSFAs via minimizing the estimated error of MSFAs. Our MSFA optimization method can select filters from off-the-shelf candidate filter sets while assigning the selected filters to the designed MSFA. Experimental results on three datasets show that the proposed method is more efficient, flexible, and can design MSFAs with lower spectral construction errors when compared with existing state-of-the-art methods. The MSFAs designed by our method show better performance than others even using different spectral reconstruction methods.

In this manuscript, an optimal linear phase finite impulse response (FIR) filter is designed using water strider optimization algorithm and implemented in the field programmable gate array (FPGA). The initiative behind the linear phase FIR filter design is “to estimate the coefficients of optimum filter.” Here, the water strider optimization algorithm is proposed to evaluate the optimal filter coefficients (LPFIR-WSOA filter). The proposed LPFIR-WSOA filter attains 32.57, 19.09, 28.07, 27.42, 24.91 and 12.72% lower maximum pass ripple compared with the existing linear phase FIR filter. Finally, the proposed LPFIR-WSOA filter is implemented in FPGA for real-time application with the target families of Virtex 6 and Virtex 7. For target FPGA families Virtex 6, the FPGA-LPFIR-WSOA filter provides 16.7910, 15.074 and 18.065% lower maximum clock frequency (MHz); 62.3837, 41.9554 and 56.078% lower delay; and 23.7172, 20.324 and 26.417% lower memory usage compared with the existing LPFIR filters like global best steered quantum-inspired cuckoo search algorithm in FPGA (FPGA-FIR-GQICSA), modified artificial bee colony optimization-based FIR filter design in FPGA (FPGA-FIR-MABCO) and hybrid artificial bee colony algorithm-based FIR filter design in FPGA (FPGA-FIR-HABCA), respectively.

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64% compared to the state-of-the-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed.

Thanks to some technical progress in interferencefilter design based on different technologies, we can finally successfully implement the concept of multispectral filter array-based sensors. This article provides the relevant state-of-the-art for multispectral imaging systems and presents the characteristics of the elements of our multispectral sensor as a case study. The spectral characteristics are based on two different spatial arrangements that distribute eight different bandpass filters in the visible and near-infrared area of the spectrum. We demonstrate that the system is viable and evaluate its performance through sensor spectral simulation.

Many signal processing applications require digital filters with variable frequency characteristics, especially the filters with variable bandwidth and center frequency. Due to their linear phase and inherent stability, finite impulse response (FIR) filters are the popular choice in the majority of the applications. Once a variable cutoff frequency (VCF) FIR lowpass filter is designed, variable bandwidth and center frequency filters with bandpass/highpass/bandstop response and reconfigurable filter banks can be realized from the same. In this paper, we present a comprehensive review of the existing variable cutoff frequency FIR filter design techniques, including the developments in the recent two decades. We provide the basic concepts, design, and architectural details for each of these techniques and the significant developments/incremental works thereof. Qualitative, as well as quantitative comparisons, are provided to assist the reader in choosing the most suitable VCF filter design technique for a particular application.

Finite Impulse Response (FIR) filters are widely used in biomedical, communication and audio signal processing applications due to their various advantages such as guaranteed stability and linear phase. The intelligent signal processing application with complex industrial systems can be implemented with the help of FIR filter design. In recent days, the design of the FIR filters is mainly controlled by the multiplication operations that lead to huge hardware utilization and delay. Therefore, the modified FIR filter is required to be developed with optimal multiplier and adder for improving the better performance in terms of hardware resource utilization and delay. In this paper, the 8-tap Fast FIR Algorithm (FFA) filter is proposed for decreasing hardware utilization. Here, the logical elements of the FFA filter are minimized using the Vedic multiplier (VM) and Carry Lookahead Adder (CLA). Additionally, the reduction in the logical elements leads to minimizing the delay which leads to increases in the operating frequency of the 8-tap FFA filter. Moreover, this proposed FFA-VM-CLA system is also analyzed in the Field Programmable Gate Array (FPGA) device of Spartan 6. The performance of the FFA-VM-CLA system is analyzed in terms of number of slice registers, flip flops, number of slices, Look Up Tables (LUTs), number of logical elements, slices, bonded Input/Output Block (IOB), delay, power and operating frequency. There are five different existing methods used to evaluate the FFA-VM-CLA system such as FIR-TDO, FIR-DNS, SLU-OBC-DA-FIR, FPPE and BP-FIR. The LUT of the FFA-VM-CLA system designed in the Virtex 5 is 174, it is less when compared to the FIR-TDO and SLU-OBC-DA-FIR.

This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)‐based reconfigurable buffer insertion strategy for optimizing field‐programmable gate array (FPGA) performance. The proposed strategy greatly enhances the debugging process by offering a systematic approach for error discovery, so ensuring that the FPGA functions with diminished complexity and increased dependability. Additionally, a reconfigurable decision tree generation (DTG)‐finite impulse response (FIR) filter design is shown to optimize circuit area, resulting in a decrease in the quantity of stored memory look‐up tables (LUTs). The substantial enhancement in power efficiency and area attained by using 4 LUTs in place of 6 LUTs. This work executes and verifies the register‐transfer level (RTL) functionality by operating with 16 taps. This idea depends on the usage of an FSM controller for the utilization of a common buffer. This buffer eliminates the usage of 16 distinct buffers by sharing all 16 taps in order to identify errors. With this approach, the simplified design and overall efficiency are improved. This approach achieves improved debug capabilities with a single common buffer by eliminating usage of multiple buffers. The hardware complexity of the circuit is decreased substantially by using this proposed model. This model proves that the suggested FSM‐based buffer insertion and reconfigurable FIR filter design improve computational efficiency and FPGA area optimization, positioning it as a viable alternative for forthcoming FPGA‐based designs.

This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.

This paper presents a tracking algorithm for joint estimation of direction of arrival (DOA) and polarization parameters, which exhibit dynamic behavior due to the movement of signal source carriers. The proposed algorithm addresses the challenge of real-time estimation in multi-target scenarios with an unknown number. This algorithm is built upon the Multi-target Multi-Bernoulli (MeMBer) filter algorithm, which makes use of a sensor array called Circular Orthogonal Double-Dipole (CODD). The algorithm begins by constructing a Minimum Description Length (MDL) principle, taking advantage of the characteristics of the polarization-sensitive array. This allows for adaptive estimation of the number of signal sources and facilitates the separation of the noise subspace. Subsequently, the joint parameter Multiple Signal Classification (MUSIC) spatial spectrum function is employed as the pseudo-likelihood function, overcoming the limitations imposed by unknown prior information constraints. To approximate the posterior distribution of MeMBer filters, Sequential Monte Carlo (SMC) method is utilized. The simulation results demonstrate that the proposed algorithm achieves excellent tracking accuracy in joint DOA-polarization parameter estimation, whether in scenarios with known or unknown numbers of signal sources. Moreover, the algorithm demonstrates robust tracking convergence even under low Signal-to-Noise Ratio (SNR) conditions.

In this paper we propose a new algorithm for real-time filtering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the filtering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small field-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray fluoroscopy as a case study. We use IIR filters for time filtering, which largely simplifies hardware cost with respect to previous FIR filter-based implementations. A conditional reset is implemented in the IIR filter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial filtering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR filter hardware implementation is optimized by using a novel technique, based on Steiglitz–McBride iterative method, to calculate fixed-point filter coefficients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time filtering of 1024 × 1024@49fps video stream. For comparison, a previous FIR filter-based implementation, on the same FPGA, in the same conditions and constraints (1024 × 1024@49fps), requires the 80% of the logic resources of the FPGA.