Asset Details
MbrlCatalogueTitleDetail
Do you wish to reserve the book?
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
by
Castellano, G
, Napoli, E
, Petra, N
, Esposito, D
, Andreozzi, E
, Bifulco, P
, Strollo, A G M
, De Caro, D
, Cesarelli, M
in
Adaptive filters
/ Algorithms
/ Field programmable gate arrays
/ FIR filters
/ Fluoroscopy
/ Hardware
/ IIR filters
/ Noise
/ Noise reduction
/ Real time
/ Spatial filtering
/ State of the art
/ Video data
2019
Hey, we have placed the reservation for you!
By the way, why not check out events that you can attend while you pick your title.
You are currently in the queue to collect this book. You will be notified once it is your turn to collect the book.
Oops! Something went wrong.
Looks like we were not able to place the reservation. Kindly try again later.
Are you sure you want to remove the book from the shelf?
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
by
Castellano, G
, Napoli, E
, Petra, N
, Esposito, D
, Andreozzi, E
, Bifulco, P
, Strollo, A G M
, De Caro, D
, Cesarelli, M
in
Adaptive filters
/ Algorithms
/ Field programmable gate arrays
/ FIR filters
/ Fluoroscopy
/ Hardware
/ IIR filters
/ Noise
/ Noise reduction
/ Real time
/ Spatial filtering
/ State of the art
/ Video data
2019
Oops! Something went wrong.
While trying to remove the title from your shelf something went wrong :( Kindly try again later!
Do you wish to request the book?
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
by
Castellano, G
, Napoli, E
, Petra, N
, Esposito, D
, Andreozzi, E
, Bifulco, P
, Strollo, A G M
, De Caro, D
, Cesarelli, M
in
Adaptive filters
/ Algorithms
/ Field programmable gate arrays
/ FIR filters
/ Fluoroscopy
/ Hardware
/ IIR filters
/ Noise
/ Noise reduction
/ Real time
/ Spatial filtering
/ State of the art
/ Video data
2019
Please be aware that the book you have requested cannot be checked out. If you would like to checkout this book, you can reserve another copy
We have requested the book for you!
Your request is successful and it will be processed during the Library working hours. Please check the status of your request in My Requests.
Oops! Something went wrong.
Looks like we were not able to place your request. Kindly try again later.
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
Journal Article
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
2019
Request Book From Autostore
and Choose the Collection Method
Overview
In this paper we propose a new algorithm for real-time filtering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the filtering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small field-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray fluoroscopy as a case study. We use IIR filters for time filtering, which largely simplifies hardware cost with respect to previous FIR filter-based implementations. A conditional reset is implemented in the IIR filter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial filtering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR filter hardware implementation is optimized by using a novel technique, based on Steiglitz–McBride iterative method, to calculate fixed-point filter coefficients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time filtering of 1024 × 1024@49fps video stream. For comparison, a previous FIR filter-based implementation, on the same FPGA, in the same conditions and constraints (1024 × 1024@49fps), requires the 80% of the logic resources of the FPGA.
Publisher
Springer Nature B.V
Subject
This website uses cookies to ensure you get the best experience on our website.