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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy

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An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
Journal Article

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy

2019
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Overview
In this paper we propose a new algorithm for real-time filtering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the filtering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small field-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray fluoroscopy as a case study. We use IIR filters for time filtering, which largely simplifies hardware cost with respect to previous FIR filter-based implementations. A conditional reset is implemented in the IIR filter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial filtering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR filter hardware implementation is optimized by using a novel technique, based on Steiglitz–McBride iterative method, to calculate fixed-point filter coefficients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time filtering of 1024 × 1024@49fps video stream. For comparison, a previous FIR filter-based implementation, on the same FPGA, in the same conditions and constraints (1024 × 1024@49fps), requires the 80% of the logic resources of the FPGA.