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Reversible logic computation and optimization of reversible circuits help synthesize applications characterized by ultra‐low power consumption, including quantum information processing, the field of nanotechnology, semiconductor technology, the field of optics, and very‐large‐scale integration (VLSI), among others. Reversible logic design is a growing research subject that evaluates and applies resources in new advancements. This article provides an optimized, unique, resource‐constrained universal quantum reversible gate for nanoscale applications that perform all fundamental logic operations. Optimization and gate relocation have enhanced a published and proposed design. Quantum reversible circuits are optimized for cost and depth via template matching, gate fusion (merging) and commutation, gate decomposition, and gate elimination. These methods reduce circuit complexity and size significantly. A step‐by‐step optimization of the quantum reversible logic design is first presented. The novel quantum reversible gates MRQ1, MRQ2, and M‐BUS are implemented and verified on the IBM Qiskit platform. The proposed reversible gates’ design complexity is assessed using 13 standard Boolean expressions. Proposed quantum reversible gates demonstrate an improvement in performance, covering a range of 12.5%–72.7% over prior designs in gate count, depth, and quantum cost. Gate count improved most, impacting other parameters and demonstrating the design’s resource efficiency.

In terms of technological advancement, digital circuit design plays a vital role. Every application needs efficient designs for high-speed and low-power consumption devices. The need for resource constraint devices is overgrowing because of the increased adaptation of IoT and Wireless Sensor Networks for home and industrial automation. For any digital components for such devices, multiplier modules are essential in the digital circuit design. Effective multiplier designs have achieved the digital components' speed, delay, and power efficiency. The Vedic multiplier is considered the most efficient among the various multipliers due to its ability to process inputs in parallel. Another major challenge in digital circuit design is reducing power consumption and avoiding information loss. In terms of irreversible logic, heat is wasted during computing due to information destruction, which is not concerned with processing. To overcome this situation, reversible logic has been introduced with reversible gates. Thereby, this work aims to explore the possibility of developing reversible Vedic multipliers with reduced delay and higher power efficiency with improved design and implementation aspects. In this work, three models with Vedic Multiplier designs using different reversible logic circuits with low power, speed, and area-efficient reversible logic are proposed to address the lower hardware complexity resulting in a better speed of operations and reduction of power dissipation. The low number of adders in the Vedic multiplier diminishes area and power dissipation and increases the operational speed. The proposed reversible logic methods achieved low power consumption with zero information loss and increased delay.

An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct $W_{32}$W32, $W_{64}$W64, and $W_{128}$W128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

A new reconfigurable architecture for biomedical applications is presented in this paper. The architecture targets frequently encountered functions in biomedical signal processing algorithms thereby replacing multiple dedicated accelerators and reports low gate count. An optimized implementation is achieved by mapping methodologies to functions and limiting the required memory leading directly to an overall minimization of gate count. The proposed architecture has a simple configuration scheme with special provision for handling feedback. The effectiveness of the architecture is demonstrated on an FPGA to show implementation schemes for multiple DSP functions. The architecture has gate count of ≈ 25k and an operating frequency of 46.9 MHz.

In this study, the authors present a configurable architecture having gate count of $ \\simeq 3.2k$≃3.2k and on the fly reconfigurability for low-power biomedical applications such as QRS detection, ExG processing etc. The proposed architecture is a light-weight co-processor that supports on-node digital signal and image processing functions potentially eliminating the power consumed by radios in wireless sensor node and body sensor network. The architecture consists of a 3 × 3 array of register units along with adaptive memory with configurable data path. The architecture can be configured on-the-fly for seven functions with the current memory structure. However, more number of functions can be targeted with increased memory. They demonstrate the realisation of Pan–Tompkins algorithm commonly used for QRS detection on the proposed architecture using the reconfigurability. This work offers $ \\approx 4 \\times $≈4× reduced area and $2.3 \\times $2.3× increase in performance with respect to the existing contemporary literature.

A novel low-complexity and high-quality colour demosaicking algorithm is proposed for very large-scale integration (VLSI) implementation for real-time video applications. It consists of a boundary detector, a boundary mirror model and five green and red–blue colour interpolation models. Two of the five interpolation models can be selected adaptively according to boundary and position information. In addition, a boundary mirror machine and identical direction technique were used to improve the qualities of the reconstructed images. To reduce the hardware cost, memory requirement and power consumption, a hardware-sharing technique and register bank design were used to realise the proposed algorithm. The VLSI architecture of this work contains only 2.9 K gate counts and its core area is 35 966 μm2 synthesised by a 0.18 μm CMOS process. The synthesised results show that this design performs an operating frequency of 100 MHz processing rate by consuming only 1.83 mW. Compared with the previous low-complexity designs, this work not only reduces at least 48.2% of gate counts and 96.7% of power consumption but also improves the average CPSNR quality by more than 0.78 dB.

A novel combinational digital device for finding maximum magnitude among the ‘n’ input numbers is proposed. This maximum magnitude generator (MaxMG) generates maximum magnitude as an output by utilising the bit by bit approach from multiple input (multi-bit) values simultaneously. MaxMG generates output from most significant bit (MSB) to least significant bit (LSB) in parallel, which utilises a minimum number of gate counts among the multi-bit of multiple input values. The minimum magnitude generator is also derived by applying the dual function to the MaxMG. The proposed design is implemented using Synopsys 90 nm generic library and RTL is written using Verilog HDL. The performance of the proposed design is compared with a rank based Kth max selection algorithm, a parallel tree based maximum generator utilised comparator-multiplexer combination, an array-based maximum finder (AB) and improved quad tree (IQT). The bit by bit parallel processing at the inputs – from MSB to LSB, and the simple architecture utilising a minimum number of gates, makes the proposed design more energy efficient when compared with the Kth max algorithm, the tree based maximum finder, the AB based maximum finder, and the IQT architecture.

A design for an integer motion estimator of high-efficiency video coding (HEVC) is presented. HEVC supports the 64 × 64 coding tree unit, the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode in a high compression ratio. These features require a structure of integer motion estimation that is more complex than that of H.264/AVC. The new structures of a memory read controller and a sum of absolute difference (SAD) summation block are proposed. The new memory read controller reduces the internal memory read time, and the new SAD summation block structure supports the recursive quad-tree coding unit structure and the asymmetric motion-partitioning mode. The proposed design is implemented in Verilog HDL and synthesised using the 65 nm CMOS technology. The gate count is 3.56 M, and the internal static random access memory is about 20 kbyte. The operation frequency is 250 MHz when a 4 K-Ultra high definition (UHD) (3840 × 2160P at 30 Hz) sized video is encoded.

This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.